# US 2019/0355751 A1 · Wiring layer and manufacturing method therefor

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- Number: US 2019/0355751 A1
- Document ID: US20190355751A1
- Status: Published application
- Kind: A1
- Application number: 16/423,884
- Filed: 2019-05-28
- Published: 2019-11-21
- Earliest claimed: 2014-10-01
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd
- Inventors: Yutaka OKAZAKI; Tomoaki Moriwaka; Shinya SASAGAWA; Takashi OHTSUKI
- Web page: https://patentgrep.com/patent/US20190355751A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10D 30/0312: {characterised by the gate electrodes}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

## Claims

### Claim 1

(canceled)

### Claim 2

A method for manufacturing a semiconductor device, comprising:
forming a first insulator;
forming a second insulator over the first insulator;
forming an opening in the second insulator;
forming a first conductor over the second insulator and in the opening;
forming a second conductor over the first conductor;
after forming the second conductor, performing a first polishing treatment to remove portions of the first and second conductors above a top surface of the second insulator;
forming a third conductor over the second conductor and the second insulator; and
performing a second polishing treatment on the third conductor until a part of the second insulator is exposed,
wherein a part of the first insulator is exposed in the opening,
wherein, after the second polishing treatment, a top of a side surface of the first conductor is at a level lower than or equal to a top level of the opening,
wherein, after the second polishing treatment, a top surface of the second conductor is at a level lower than or equal to a level of the top of the side surface of the first conductor,
wherein the third conductor is in contact with the top surface of the second conductor,
wherein the first conductor comprises a metal element and nitrogen,
wherein the third conductor comprises a metal element and nitrogen, and
wherein the second conductor comprises tungsten.

### Claim 3 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, wherein the first conductor and the third conductor allow less oxygen to pass therethrough than the second conductor.

### Claim 4 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, wherein a bottom surface of the first conductor is in contact with an upper surface of the first insulator in the opening.

### Claim 5 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, wherein an upper surface of the first conductor at a bottom of the opening is above a top surface of the first insulator outside the opening.

### Claim 6 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2,
wherein the third conductor is in contact with an inside side surface of the first conductor.

### Claim 7 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, wherein a top surface of the third conductor is a concave surface.

### Claim 8 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, further comprising forming a transistor comprising an oxide semiconductor layer over the third conductor,
wherein the oxide semiconductor layer and the third conductor overlap with each other.

### Claim 9 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2, further comprising:
forming a third insulator over the third conductor; and
forming a fourth conductor over the third insulator;
wherein the fourth conductor, the third insulator, and the third conductor constitutes a capacitor.

### Claim 10 (depends on 2)

The method for manufacturing a semiconductor device according to claim 2,
wherein the first insulator is formed over a third insulator.

### Claim 11

A method for manufacturing a semiconductor device, comprising:
forming a first insulator;
forming a second insulator over the first insulator;
forming an opening in the second insulator;
forming a first conductor over the second insulator and in the opening;
forming a second conductor over the first conductor;
after forming the second conductor, performing a first polishing treatment to remove portions of the first and second conductors above a top surface of the second insulator;
forming a third conductor over the second conductor and the second insulator; and
performing a second polishing treatment on the third conductor until a part of the second insulator is exposed,
wherein a part of the first insulator is exposed in the opening,
wherein, after the second polishing treatment, a top of a side surface of the first conductor is at a level lower than or equal to a top level of the opening,
wherein, after the second polishing treatment, a top surface of the second conductor is at a level lower than or equal to a level of the top of the side surface of the first conductor,
wherein the third conductor is in contact with the top surface of the second conductor,
wherein the first conductor comprises titanium and nitrogen,
wherein the third conductor comprises titanium and nitrogen, and
wherein the second conductor comprises tungsten.

### Claim 12 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11, wherein the first conductor and the third conductor allow less oxygen to pass therethrough than the second conductor.

### Claim 13 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11, wherein a bottom surface of the first conductor is in contact with an upper surface of the first insulator in the opening.

### Claim 14 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11, wherein an upper surface of the first conductor at a bottom of the opening is above a top surface of the first insulator outside the opening.

### Claim 15 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11,
wherein the third conductor is in contact with an inside side surface of the first conductor.

### Claim 16 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11, wherein a top surface of the third conductor is a concave surface.

### Claim 17 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11, further comprising forming a transistor comprising an oxide semiconductor layer over the third conductor,
wherein the oxide semiconductor layer and the third conductor overlap with each other.

### Claim 18 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11, further comprising:
forming a third insulator over the third conductor; and
forming a fourth conductor over the third insulator;
wherein the fourth conductor, the third insulator, and the third conductor constitutes a capacitor.

### Claim 19 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11,
wherein the first insulator is formed over a third insulator.

### Claim 20 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11,
wherein the first conductor is a titanium nitride film,
wherein the third conductor is a titanium nitride film, and
wherein the second insulator comprises silicon and oxygen.