# US 2019/0355745 A1 · Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells

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- Number: US 2019/0355745 A1
- Document ID: US20190355745A1
- Status: Published application
- Kind: A1
- Application number: 16/528,454
- Filed: 2019-07-31
- Published: 2019-11-21
- Earliest claimed: 2015-07-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jie Sun; Fatma Arzum Simsek-Ege
- Web page: https://patentgrep.com/patent/US20190355745A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/6314: {of a metallic layer}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

## Claims

### Claim 1

A method of forming a system, comprising:
forming an opening which extends through a gate material, through an insulative material under the gate material, and through a stack of alternating dielectric levels and conductive levels under the insulative material; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels; and
forming semiconductive material within the opening adjacent the insulative material, adjacent the gate material, adjacent the dielectric levels of the stack, and the conductive levels of the stack.

### Claim 2 (depends on 1)

The method of claim 1 further comprising forming cavities extending into the conductive levels along sidewalls of the opening.

### Claim 3 (depends on 2)

The method of claim 2 further comprising forming charge-storage structures within the cavities.

### Claim 4 (depends on 3)

The method of claim 3 wherein the charge-storage structures comprise charge-trapping material.

### Claim 5 (depends on 4)

The method of claim 4 wherein the charge-trapping material comprises silicon nitride.

### Claim 6 (depends on 4)

The method of claim 4 wherein the charge-trapping material comprises metal dots.

### Claim 7 (depends on 1)

The method of claim 1 wherein the insulative material comprises silicon dioxide and is formed utilizing plasma-enhanced chemical vapor deposition.

### Claim 8 (depends on 1)

The method of claim 1 wherein the second and third regions of the opening are about a same width as one another along the cross-section.

### Claim 9 (depends on 1)

The method of claim 1 wherein the first region is wider than the second and third regions by an amount within a range of from about 3 nm to about 25 nm.

### Claim 10 (depends on 1)

The method of claim 1 wherein the first region has a width along the cross-section within a range of from about 60 nm to about 75 nm, and wherein second and third regions have widths along the cross-section within a range of from about 55 nm to about 65 nm.