# US 2019/0355731 A1 · Method to reduce kink effect in semiconductor devices

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- Number: US 2019/0355731 A1
- Document ID: US20190355731A1
- Status: Published application
- Kind: A1
- Application number: 15/981,056
- Filed: 2018-05-16
- Published: 2019-11-21
- Earliest claimed: 2018-05-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Ling Shih; Chieh-Fei Chiu; Po-Wei Liu; Wen-Tuo Huang; Yu-Ling Hsu; Yong-Shiuan Tsair; Shih Kuang Yang
- Web page: https://patentgrep.com/patent/US20190355731A1

## CPC

- H10B 41/30: characterised by the memory core region
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/68: Floating-gate IGFETs
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 76/2041: {Photolithographic processes}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10P 50/283: {by chemical means}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
forming a pad stack over a semiconductor substrate, wherein the pad stack comprises a lower pad layer and an upper pad layer;
patterning the upper pad layer and the lower pad layer into a patterned upper pad layer and a patterned lower pad layer, respectively;
forming an isolation structure in the semiconductor substrate, wherein the isolation structure comprises a pair of isolation segments separated by the patterned upper pad layer and the patterned lower pad layer;
removing the patterned upper pad layer to form an opening between the isolation segments, wherein sidewalls of the isolation segments are slated at a first angle relative to an upper surface of the patterned lower pad layer and respectively define sides of the opening;
performing a first etch to partially remove the patterned lower pad layer exposed from the opening, and to partially remove the isolation segments through the opening so the sidewalls of the isolation segments are slanted at a second angle greater than the first angle;
performing a second etch to round the sidewalls of the isolation segments and to remove the patterned lower pad layer exposed from the opening; and
forming a floating gate in the opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein after the second etch, the opening exposes a substantially planar upper surface of the semiconductor substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first etch is a chemical oxide removal (COR) etch and the second etch is a wet etch.

### Claim 4 (depends on 3)

The method of claim 3, wherein the COR etch comprises exposing the semiconductor substrate to ammonium or hydrogen fluoride, and then heating the semiconductor substrate in a nitrogen gas environment, and wherein the wet etch comprises a diluted hydrofluoric acid (DHF) etchant.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the floating gate comprises:
depositing a conductive layer filling the opening; and
performing a chemical-mechanical planarization (CMP) process on the conductive layer, such that upper surfaces of the conductive layer and the isolation segments are substantially planar.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
forming a dielectric layer in the opening, wherein the dielectric layer continuously extends along the rounded sidewalls of the isolation segments, along an upper surface of the semiconductor substrate disposed between the rounded sidewalls of the isolation segments, and over the isolation segments, wherein the conductive layer is formed over the dielectric layer, and wherein the CMP is performed into the dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first etch increases a first width of the opening greater than a second width of the opening, wherein the first width is measured near a top of the opening and the second width is measured near a bottom of the opening.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first angle is a first acute angle and the second angle is a second acute angle.

### Claim 9 (depends on 1)

The method of claim 1, wherein the rounded sidewalls of the isolation segments extend from an upper surface of the semiconductor substrate at obtuse angles and respectively arch to upper surfaces of the isolation segments.

### Claim 10

A method for forming a semiconductor device, the method comprising:
forming a pad stack over a semiconductor substrate, wherein the pad stack comprises a lower pad layer and an upper pad layer;
patterning the upper pad layer and the lower pad layer into a patterned upper pad layer and a patterned lower pad layer, respectively;
forming an isolation structure in the semiconductor substrate, wherein the isolation structure comprises a first isolation structure segment and a second isolation structure segment separated by the patterned upper pad layer and the patterned lower pad layer;
removing the patterned upper pad layer to form an opening between the first isolation structure segment and the second isolation structure segment, wherein the opening is defined by opposing sidewalls of the first and second isolation structure segments;
performing a first etch to partially remove the patterned lower pad layer between the first and second isolation structure segments, and to partially remove the first and second isolation structure segments through the opening, wherein the first etch increases a lateral separation between the opposing sidewalls more at a top of the opening than at a bottom of the opening;
performing a second etch to arch the opposing sidewalls and to remove the patterned lower pad layer between the first and second isolation structure segments; and
forming a first floating gate between the first and second isolation structure segments.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first and second isolation structure segments are separated in a first direction, and wherein the method further comprises:
forming a second floating gate between the first and second isolation structure segments, wherein the first floating gate and the second floating gate are spaced apart in a second direction transverse the first direction and each have a substantially planar bottom surface.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming an erase gate between the first floating gate and the second floating gate.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a first select gate and a second select gate, wherein the first select gate is separated from the erase gate by the first floating gate and the second select gate is separated from the erase gate by the second floating gate.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a common source/drain region in the semiconductor substrate, wherein the common source/drain region is disposed beneath the erase gate.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
forming a first dielectric layer that lines the arched opposing sidewalls of the first and second isolation structure segments and extends over the first and second isolation structure segments, wherein the first dielectric layer has a substantially planar bottom surface between the arched opposing sidewalls of the first and second isolation structure segments;
forming a first conductive layer over the first dielectric layer; and
patterning the first conductive layer and the first dielectric layer respectively into the first floating gate and a first floating gate dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a second dielectric layer over the first conductive layer;
forming a second conductive layer over the second dielectric layer; and
patterning the second conductive layer and the second dielectric layer respectively into a control gate and a control gate dielectric layer overlying the conductive layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the patterning of the first conductive layer comprises:
performing a chemical-mechanical planarization (CMP) process on the first conductive layer, such that upper surfaces of the first conductive layer, the first dielectric layer, the first isolation structure segment, and the second isolation structure segment are substantially planar.

### Claim at position 18

18-20. (canceled)

### Claim 21

A method for forming a semiconductor device, the method comprising:
forming a control gate over a semiconductor substrate;
forming a floating gate between the control gate and the semiconductor substrate, wherein the floating gate is formed with a bottom surface extending in a first lateral direction that is substantially planar, and wherein the floating gate is formed with a pair of arching sidewalls spaced apart in a second lateral direction perpendicular to the first lateral direction;
forming a first source/drain region in the semiconductor substrate and on a first side of the floating gate;
forming an erase gate directly over the first source/drain region;
forming a select gate over the semiconductor substrate and on a second side of the floating gate opposite the first side, wherein the first side and the second side are spaced apart in the first lateral direction; and
forming a second source/drain region in the semiconductor substrate and on the second side of the floating gate.

### Claim 22 (depends on 21)

The method of claim 21, further comprising:
before the floating control gate is formed, forming an isolation structure in the semiconductor substrate; and
forming a floating gate dielectric between the floating gate and the isolation structure.

### Claim 23 (depends on 22)

The method of claim 22, wherein the floating gate dielectric is formed with an upper surface that is substantially co-planar with both an upper surface of the floating gate and an upper surface of the isolation structure.