# US 2019/0355718 A1 · Reverse-conducting insulated gate bipolar transistor

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- Number: US 2019/0355718 A1
- Document ID: US20190355718A1
- Status: Published application
- Kind: A1
- Application number: 16/362,165
- Filed: 2019-03-22
- Published: 2019-11-21
- Earliest claimed: 2018-05-18
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Hayato Nakano; Keiichi Higuchi; Akihiro Osawa
- Web page: https://patentgrep.com/patent/US20190355718A1

## CPC

- H10D 84/406: {Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 12/441: {Vertical IGBTs}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 64/232: {Emitter electrodes for IGBTs}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10W 70/461: {specially adapted for cooling}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.

## Claims

### Claim 1

A reverse-conducting semiconductor device comprising:
a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided above the top surface of the semiconductor chip, covering an area, in which the transistor regions and the diode regions are provided; and
a wiring member having a flat-plate portion having a rectangular-shape, which is metallurgically jointed to the upper-electrode via a joint member above the diode regions; wherein
the transistor regions, each of which has a stripe-shape extending in parallel to the first side in the plan view, implement main current paths for conducting main current in a direction perpendicular to the top surface of the semiconductor chip,
the diode regions, each of which has a stripe-shape extending parallel to the first side in the plan view, implement flyback paths for conducting reverse current in a direction perpendicular to the top surface of the semiconductor chip, and
the wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.

### Claim 2 (depends on 1)

The reverse-conducting semiconductor device according to claim 1, wherein the semiconductor chip has a rectangular-shape in the plan view, and the first side is longer than the second side.

### Claim 3 (depends on 2)

The reverse-conducting semiconductor device according to claim 2, wherein the flyback paths through the diode regions extends parallel to each other to sandwich a part of the main current paths through the transistor regions.

### Claim 4 (depends on 1)

The reverse-conducting semiconductor device according to claim 1, wherein the conductive wall is configured to electrically connect to an external circuit.

### Claim 5 (depends on 1)

The reverse-conducting semiconductor device according to claim 1, wherein all of the diode regions are covered with the flat-plate portion in the plan view.

### Claim 6 (depends on 1)

The reverse-conducting semiconductor device according to claim 1, wherein an area of the diode regions covered with the flat-plate portion is 20 percent or more and 60 percent or less with respect to an area of the flat-plate portion in the plan view.