# US 2019/0355705 A1 · Method for manufacturing display array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355705 A1 - Document ID: US20190355705A1 - Status: Published application - Kind: A1 - Application number: 16/232,064 - Filed: 2018-12-26 - Published: 2019-11-21 - Earliest claimed: 2018-05-16 - Assignees: Industrial Technology Research Institute - Applicants: Industrial Technology Research Institute - Inventors: Ming-Hsien Wu; Chia-Hsin Chao; Yen-Hsiang Fang - Web page: https://patentgrep.com/patent/US20190355705A1 ## CPC - H10W 90/00: Package configurations - H10D 86/021: {of multiple TFTs} - H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout} - H10H 20/8162: {Current-blocking structures} - H10H 20/831: characterised by their shape - H10H 20/84: Coatings, e.g. passivation layers or antireflective coatings - H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract A method for manufacturing a display array includes the following steps: providing a substrate and forming a semiconductor stacked layer on the substrate; forming an insulating layer and a plurality of electrode pads on an outer surface of the semiconductor stacked layer, the insulating layer and the electrode pads directly contacting the semiconductor stacked layer, wherein the insulating layer has a plurality of openings, and the electrode pads are respectively located in the openings of the insulating layer and separated by the insulating layer; and transferring the semiconductor stacked layer, the insulating layer and the electrode pads from the substrate to a driving backplane, wherein the electrode pads are respectively electrically connected to a portion of the semiconductor stacked layer and the driving backplane through the openings of the insulating layer to form a plurality of light emitting regions in the semiconductor stacked layer. ## Claims ### Claim 1 A method for manufacturing a display array, comprising: providing a substrate and forming a semiconductor stacked layer on the substrate; forming an insulating layer and a plurality of electrode pads on an outer surface of the semiconductor stacked layer, the insulating layer and the electrode pads directly contacting the semiconductor stacked layer, wherein the insulating layer has a plurality of openings, and the electrode pads are respectively located in the openings of the insulating layer and separated by the insulating layer; and transferring the semiconductor stacked layer, the insulating layer and the electrode pads from the substrate to a driving backplane, wherein the electrode pads are respectively electrically connected to a portion of the semiconductor stacked layer and the driving backplane through the openings of the insulating layer to form a plurality of light emitting regions in the semiconductor stacked layer, and the adjacent light emitting regions in the semiconductor stacked layer are not patterned. ### Claim 2 (depends on 1) The method for manufacturing the display array as claimed in claim 1, wherein the electrode pads directly contact the insulating layer. ### Claim 3 (depends on 1) The method for manufacturing the display array as claimed in claim 1, further comprising: forming an electrode layer on the semiconductor stacked layer; and forming a light absorbing layer on the electrode layer, the electrode layer being located between the light absorbing layer and the semiconductor stacked layer, wherein the light absorbing layer has a plurality of openings, the light emitting regions are located between the openings of the light absorbing layer and the electrode pads. ### Claim 4 (depends on 3) The method for manufacturing the display array as claimed in claim 3, wherein the electrode layer has a plurality of openings, and the openings of the electrode layer are located between the openings of the light absorbing layer and the light emitting regions. ### Claim 5 (depends on 3) The method for manufacturing the display array as claimed in claim 3, wherein a light emitting area of the light emitting regions in the semiconductor stacked layer is greater than or equal to an area occupied by the openings of the light absorbing layer. ### Claim 6 (depends on 3) The method for manufacturing the display array as claimed in claim 3, wherein an area occupied by the openings of the light absorbing layer is greater than an area occupied by the openings of the insulating layer. ### Claim 7 (depends on 3) The method for manufacturing the display array as claimed in claim 3, wherein a covering area of the light absorbing layer on the semiconductor stacked layer is smaller than a covering area of the insulating layer on the semiconductor stacked layer. ### Claim 8 (depends on 1) The method for manufacturing the display array as claimed in claim 1, wherein the insulating layer comprises a first insulating layer and a second insulating layer, and forming the insulating layer and the electrode pads on the semiconductor stacked layer further comprises: forming the first insulating layer on the semiconductor stacked layer, wherein the first insulating layer has a plurality of openings; disposing the electrode pads in the openings of the first insulating layer; and filling the second insulating layer between the electrode pads, wherein the first insulating layer is located between the second insulating layer and the semiconductor stacked layer. ### Claim 9 (depends on 1) The method for manufacturing the display array as claimed in claim 1, further comprising: forming at least one electrically insulating part in the semiconductor stacked layer through ion implantation, so as to electrically isolate the light emitting regions from each other, wherein an impedance of the at least one electrically insulating part is greater than 100 times of an impedance of the light emitting regions. ### Claim 10 (depends on 9) The method for manufacturing the display array as claimed in claim 9, wherein the at least one electrically insulating part is distributed with a depth less than or equal to a thickness of the semiconductor stacked layer. ### Claim 11 (depends on 1) The method for manufacturing the display array as claimed in claim 1, wherein transferring the semiconductor stacked layer, the insulating layer, and the electrode pads from the substrate to the driving backplane comprises: disposing the semiconductor stacked layer on the driving backplane; and removing the substrate, wherein the insulating layer is located between the semiconductor stacked layer and the driving backplane. ### Claim 12 (depends on 1) The method for manufacturing the display array as claimed in claim 1, wherein transferring the semiconductor stacked layer, the insulating layer, and the electrode pads from the substrate to the driving backplane comprises: removing the substrate to dispose the semiconductor stacked layer, the insulating layer, and the electrode pads on the driving backplane, wherein the semiconductor stacked layer is located between the insulating layer and the driving backplane. ### Claim 13 (depends on 1) The method for manufacturing the display array as claimed in claim 1, wherein transferring the semiconductor stacked layer, the insulating layer, and the electrode pads from the substrate to the driving backplane comprises: forming an adhesive layer on the electrode pads; and disposing the adhesive layer to the driving backplane. ### Claim 14 (depends on 1) The method for manufacturing the display array as claimed in claim 1, further comprising: providing a plurality of color converters and disposing the color converters on the semiconductor stacked layer. ### Claim 15 (depends on 1) The method for manufacturing the display array as claimed in claim 1, wherein an arrangement pitch of two adjacent light emitting regions of the light emitting regions is less than or equal to 20 micrometers.