# US 2019/0355697 A1 · Electronic package for high-data rate communication applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355697 A1 - Document ID: US20190355697A1 - Status: Published application - Kind: A1 - Application number: 16/398,228 - Filed: 2019-04-29 - Published: 2019-11-21 - Earliest claimed: 2018-05-18 - Applicants: Mediatek Inc. - Inventors: Min-Chen Lin; Yi-Hui Lee; Che-Ya Chou; Nan-Cheng Chen - Web page: https://patentgrep.com/patent/US20190355697A1 ## CPC - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 70/63: Vias, e.g. via plugs - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/655: Fan-out layouts - H10W 72/29: Bond pads specially adapted therefor - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block. ## Claims ### Claim 1 An electronic package, comprising: a package substrate of a rectangular shape; and a chip package comprising a first high-speed interface circuit die, mounted on a top surface of the package substrate, wherein the chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. ### Claim 2 (depends on 1) The electronic package according to claim 1, wherein the top surface of the package substrate is partitioned into four quadrants by two orthogonal axes in a two-dimensional plane. ### Claim 3 (depends on 2) The electronic package according to claim 2, wherein the first high-speed interface circuit die comprises a first edge directly facing a vertex of the package substrate, wherein a first row of input/output (I/O) pads is disposed along the first edge. ### Claim 4 (depends on 3) The electronic package according to claim 3, wherein the first high-speed interface circuit die comprises a second edge that is perpendicular to the first edge, wherein a second row of input/output (I/O) pads is disposed along the second edge. ### Claim 5 (depends on 4) The electronic package according to claim 4, wherein a first group of solder balls is arranged along two sides joined at said vertex of the package substrate, and wherein said first row of I/O pads is electrically connected to the first group of solder balls through a plurality first traces, respectively, within one of the four quadrants on the top surface of the package substrate. ### Claim 6 (depends on 5) The electronic package according to claim 5, wherein a second group of solder balls is arranged along one of said two sides joined at said vertex of the package substrate, and wherein said second row of I/O pads is electrically connected to the second group of solder balls through a plurality second traces, respectively, within said one of the four quadrants on the top surface of the package substrate. ### Claim 7 (depends on 1) The electronic package according to claim 1, wherein the first high-speed interface circuit die comprises a first Serializer/Deserializer (SerDes) circuit block. ### Claim 8 (depends on 1) The electronic package according to claim 1 further comprising: a second high-speed interface circuit die in proximity to the first high-speed interface circuit die. ### Claim 9 (depends on 8) The electronic package according to claim 8, wherein the second high-speed interface circuit die comprises a second Serializer/Deserializer (SerDes) circuit block. ### Claim 10 (depends on 8) The electronic package according to claim 8, wherein the first high-speed interface circuit die is electrically connected to the second high-speed interface circuit die through a redistribution layer (RDL) structure. ### Claim 11 An electronic package, comprising: a package substrate of a rectangular shape; and a chip package comprising a first high-speed interface circuit die, mounted on a top surface of the package substrate, wherein the first high-speed interface circuit die comprises a first edge directly facing a vertex of the package substrate, wherein a first row of input/output (I/O) pads is disposed along the first edge. ### Claim 12 (depends on 11) The electronic package according to claim 11, wherein the top surface of the package substrate is partitioned into four quadrants by two orthogonal axes in a two-dimensional plane. ### Claim 13 (depends on 12) The electronic package according to claim 12, wherein the chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. ### Claim 14 (depends on 13) The electronic package according to claim 13, wherein the first high-speed interface circuit die comprises a second edge that is perpendicular to the first edge, wherein a second row of input/output (I/O) pads is disposed along the second edge. ### Claim 15 (depends on 14) The electronic package according to claim 14, wherein a first group of solder balls is arranged along two sides joined at said vertex of the package substrate, and wherein said first row of I/O pads is electrically connected to the first group of solder balls through a plurality first traces, respectively, within one of the four quadrants on the top surface of the package substrate. ### Claim 16 (depends on 15) The electronic package according to claim 15, wherein a second group of solder balls is arranged along one of said two sides joined at said vertex of the package substrate, and wherein said second row of I/O pads is electrically connected to the second group of solder balls through a plurality second traces, respectively, within said one of the four quadrants on the top surface of the package substrate. ### Claim 17 (depends on 11) The electronic package according to claim 11, wherein the first high-speed interface circuit die comprises a first Serializer/Deserializer (SerDes) circuit block. ### Claim 18 (depends on 11) The electronic package according to claim 11 further comprising: a second high-speed interface circuit die in proximity to the first high-speed interface circuit die. ### Claim 19 (depends on 18) The electronic package according to claim 18, wherein the second high-speed interface circuit die comprises a second Serializer/Deserializer (SerDes) circuit block. ### Claim 20 (depends on 18) The electronic package according to claim 18, wherein the first high-speed interface circuit die is electrically connected to the second high-speed interface circuit die through a redistribution layer (RDL) structure.