# US 2019/0355696 A1 · 3dic structure and method of manufacturing the same

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- Number: US 2019/0355696 A1
- Document ID: US20190355696A1
- Status: Published application
- Kind: A1
- Application number: 15/980,676
- Filed: 2018-05-15
- Published: 2019-11-21
- Earliest claimed: 2018-05-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Tzuan-Horng Liu; Hsien-Wei Chen; Jiun-Heng Wang; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US20190355696A1

## CPC

- H10W 90/00: Package configurations
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 72/073: {of die-attach connectors}
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/853: {On the same surface}
- H10W 72/9413: {on encapsulations}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/016: {Cleaning}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A 3DIC structure includes a first die and a second die on a substrate and a bonding die. The boding die is electrically bonded to the first die and the second die. The bonding die covers a portion of a top surface of a scribe region between the first die and the second die.

## Claims

### Claim 1

A 3DIC structure, comprising:
a first die and a second die on a substrate; and
a bonding die electrically bonded to the first die and the second die;
wherein the bonding die covers a portion of a top surface of a scribe region between the first die and the second die,
wherein top surfaces of the first die and the second die are partially covered by the bonding die, and a portion of the top surface of the first die and a portion of the top surface of the second die are exposed by the bonding die.

### Claim 2 (depends on 1)

The 3DIC structure of claim 1, wherein the scribe region comprises a portion of the substrate.

### Claim 3 (depends on 1)

The 3DIC structure of claim 1, wherein the bonding die is bonded to the first die and the second die through a hybrid bonding structure.

### Claim 4 (depends on 3)

The 3DIC structure of claim 3, wherein the hybrid bonding structure comprises:
a first bonding structure of the first die, comprising a first conductive structure and a first dielectric structure;
a second bonding structure of the second die, comprising a second conductive structure and a second dielectric structure; and
a third bonding structure of the bonding die, comprising a plurality of bonding pads and a dielectric layer surrounding the bonding pads,
wherein the plurality of bonding pads are bonded to the first conductive structure and the second conductive structure, the dielectric layer is bonded to the first dielectric structure and the second dielectric structure.

### Claim 5 (depends on 4)

The 3DIC structure of claim 4, wherein the first conductive structure of the first bonding structure is electrically connected to an interconnect structure of the first die.

### Claim 6 (depends on 5)

The 3DIC structure of claim 5, wherein the first conductive structure of the first bonding structure is landing on a top metal feature of the interconnect structure.

### Claim 7 (depends on 5)

The 3DIC structure of claim 5, wherein the first die further comprises a pad on the interconnect structure, the first conductive structure is landing on the pad and is electrically connected to the interconnect structure through the pad.

### Claim 8 (depends on 1)

The 3DIC structure of claim 1, wherein the first conductive structure comprises a first via and a second via on the first via, a diameter of the second via is larger than a diameter of the first via.

### Claim 9 (depends on 1)

The 3DIC structure of claim 1, wherein an area of a top surface of the first conductive structure is equal to or larger than an area of a bottom surface of the first conductive structure.

### Claim 10

A 3DIC structure, comprising:
a plurality of dies on a substrate arranged in an array, wherein portions of the substrate are located in scribe regions laterally between the plurality of dies;
a bonding die across the scribe region and electrically bonded to the plurality of dies;
a gap fill structure on the plurality of dies and on sides of the bonding die;
a redistribution layer (RDL) on the gap fill structure, electrically connected to the plurality of the dies through a plurality of through dielectric vias (TDVs),
wherein the plurality of dies are electrically connected to each other through the bonding die, the TDVs, and the RDL,
wherein top surfaces of the plurality of dies are partially covered by the bonding die, and portions of the top surfaces of the plurality of dies are exposed by the bonding die and covered by the gap fill structure.

### Claim 11 (depends on 10)

The 3DIC structure of claim 10, wherein the bonding die is bonded to two adjacent dies of the plurality of dies, and across the scribe region between the two adjacent dies.

### Claim 12 (depends on 10)

The 3DIC structure of claim 10, wherein the bonding die is bonded to four adjacent dies arranged in a 2×2 array of the plurality of dies and covers the top surface of a crisscross portion of the scribe regions between the four adjacent dies.

### Claim 13 (depends on 10)

The 3DIC structure of claim 10, wherein the bonding die comprises a plurality of bonding dies, and sizes of the plurality of bonding dies are the same or different.

### Claim 14 (depends on 10)

The 3DIC structure of claim 10, wherein the bonding die is in contact with a top surface of the scribe region.

### Claim 15

A method of manufacturing a 3DIC structure, comprising:
bonding a plurality of bonding dies to a plurality of dies in a first region of a wafer, wherein each of the bonding dies is bonded to at least two of the dies;
forming a gap fill structure on the wafer and on sides of the bonding dies;
forming a RDL on the gap fill structure, wherein the plurality of dies are electrically connected to each other through the RDL and the bonding dies;
performing a die saw process on the wafer to separate the plurality of dies in the first region from a second region other than the first region of the wafer,
wherein top surfaces of the plurality of dies are partially covered by the plurality of bonding dies, and portions of the top surfaces of the plurality of dies are exposed by the plurality of bonding dies and covered by the gap fill structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein the bonding the plurality of bonding dies to the plurality of dies is performed by a hybrid bonding process.

### Claim 17 (depends on 16)

The method of claim 16, wherein the hybrid bonding process comprises:
bonding a plurality of bonding pads of the bonding die to conductive structures of the dies; and
bonding a dielectric layer of the bonding die to dielectric structures of the dies.

### Claim 18 (depends on 17)

The method of claim 17, wherein the bonding die is further bonded to an upper portion of a scribe region between the dies.

### Claim 19 (depends on 15)

The method of claim 15, further comprising forming a plurality of TDVs in the gap fill structure.

### Claim 20 (depends on 15)

The method of claim 15, wherein the forming the plurality of TDVs is performed before or after the gap fill structure is formed.