# US 2019/0355695 A1 · Semiconductor Device and Method of Forming SIP with Electrical Component Terminals Extending Out from Encapsulant

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0355695 A1
- Document ID: US20190355695A1
- Status: Published application
- Kind: A1
- Application number: 16/531,593
- Filed: 2019-08-05
- Published: 2019-11-21
- Earliest claimed: 2016-08-31
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC Pte. Ltd.
- Inventors: JinHee Jung; OhHan Kim; InSang Yoon
- Web page: https://patentgrep.com/patent/US20190355695A1

## CPC

- H10W 72/0198: {batch processes}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/072: {of bump connectors}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 46/301: {for alignment}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.

## Claims

### Claim 1

A semiconductor device, comprising:
a carrier;
an adhesive layer formed over the carrier;
an electrical component disposed on the adhesive layer with terminals of the electrical component extending at least partially into the adhesive layer; and
an encapsulant deposited over the electrical component.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the electrical component is selected from the group consisting of a semiconductor die, discrete component, electronic module, and semiconductor package.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further including a plurality of alignment marks on the carrier or adhesive layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further including a shielding layer formed over the electrical component.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further including a shielding layer formed over the encapsulant.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further including a leadframe disposed over the carrier or adhesive layer.

### Claim 7

A semiconductor device, comprising:
a carrier;
an electrical component disposed on the carrier with terminals of the electrical component extending at least partially into the carrier; and
an encapsulant deposited over the electrical component.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the electrical component is selected from the group consisting of a semiconductor die, discrete component, electronic module, and semiconductor package.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further including a plurality of alignment marks on the carrier.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, further including a shielding layer formed over the electrical component.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, further including a shielding layer formed over the encapsulant.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, further including a leadframe disposed over the carrier.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, further including an adhesive layer formed over the carrier.

### Claim 14

A semiconductor device, comprising:
an electrical component; and
an encapsulant deposited over the electrical component with terminals of the electrical component exposed from the encapsulant.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the electrical component is selected from the group consisting of a semiconductor die, discrete component, electronic module, and semiconductor package.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further including:
a carrier; and
an adhesive layer formed over the carrier with terminals of the electrical component extending at least partially into the adhesive layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further including a plurality of alignment marks on the carrier or adhesive layer.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further including a leadframe disposed over the carrier or adhesive layer.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further including a shielding layer formed over the electrical component or encapsulant.

### Claim 20

A semiconductor device, comprising:
an electrical component including a plurality of terminals; and
an encapsulant deposited over the electrical component with the terminals of the electrical component extending from the encapsulant.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein the electrical component is selected from the group consisting of a semiconductor die, discrete component, electronic module, and semiconductor package.

### Claim 22 (depends on 20)

The semiconductor device of claim 20, further including a carrier, wherein the electrical component is disposed on the carrier.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, further including an adhesive layer formed over the carrier with the terminals of the electrical component extending at least partially into the adhesive layer.

### Claim 24 (depends on 22)

The semiconductor device of claim 22, further including a plurality of alignment marks on the carrier.

### Claim 25 (depends on 20)

The semiconductor device of claim 20, further including a shielding layer formed over the electrical component or encapsulant.