# US 2019/0355689 A1 · Single-Shot Encapsulation

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- Number: US 2019/0355689 A1
- Document ID: US20190355689A1
- Status: Published application
- Kind: A1
- Application number: 16/525,193
- Filed: 2019-07-29
- Published: 2019-11-21
- Earliest claimed: 2016-08-09
- Assignees: Semtech Corporation
- Applicants: Semtech Corporation
- Inventors: Kok Khoon Ho; Jonathan Clark; John MacLeod
- Web page: https://patentgrep.com/patent/US20190355689A1

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 14/683: {carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 70/635: {Through-vias}
- H10W 72/013: {of die-attach connectors}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10W 70/655: Fan-out layouts
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die;
a pillar bump formed over the semiconductor die;
a solder cap formed over the pillar bump; and
an encapsulant deposited over the semiconductor die, pillar bump, and solder cap, wherein a surface of the encapsulant is coplanar with a surface of the solder cap and the encapsulant contacts a back surface of the semiconductor die opposite the pillar bump.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further including a plurality of semiconductor die mechanically connected to each other by the encapsulant.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further including a first insulating layer formed over the semiconductor die, wherein the pillar bump extends into an opening of the first insulating layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further including a second insulating layer formed over the first insulating layer, wherein an opening of the second insulating layer is aligned with the opening of the first insulating layer.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the first insulating layer includes polyimide.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further including a redistribution layer connecting the pillar bump to the semiconductor die.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the solder caps include lead-free solder.

### Claim 8

A semiconductor device, comprising:
a first semiconductor die;
a pillar bump formed over the first semiconductor die;
a solder cap formed over the pillar bump; and
an encapsulant deposited over the first semiconductor die, pillar bump, and solder cap, wherein the encapsulant contacts an active surface of the first semiconductor die and a back surface of the first semiconductor die opposite the active surface.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further including a second semiconductor die disposed in the encapsulant, wherein the encapsulant extends continuously from the first semiconductor die to the second semiconductor die.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further including a printed circuit board, wherein the solder cap is bonded to a conductive trace or contact pad of the printed circuit board.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein a surface of the encapsulant is coplanar with a surface of the solder cap.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further including a first insulating layer formed over the first semiconductor die, wherein the pillar bump extends through an opening of the first insulating layer to contact the first semiconductor die.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a footprint of the opening is smaller than a footprint of the pillar bump.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further including a second insulating layer formed over the first semiconductor die and extending into the opening of the first insulating layer.

### Claim 15

A semiconductor device, comprising:
a semiconductor die;
a pillar bump formed over the semiconductor die;
a solder cap formed over the pillar bump; and
an encapsulant deposited over the semiconductor die, pillar bump, and solder cap.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a surface of the encapsulant is coplanar with a surface of the solder cap.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further including a substrate, wherein the encapsulant contacts the substrate.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, further including a redistribution layer formed between the semiconductor die and pillar bump.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further including a plurality of semiconductor die mechanically connected to each other by the encapsulant.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, further including a substrate, wherein the plurality of semiconductor die are mechanically connected to the substrate by the solder.