# US 2019/0355680 A1 · Semiconductor Device and Method of Manufacture

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- Number: US 2019/0355680 A1
- Document ID: US20190355680A1
- Status: Published application
- Kind: A1
- Application number: 16/185,749
- Filed: 2018-11-09
- Published: 2019-11-21
- Earliest claimed: 2018-05-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Po-Yao Chuang; Po-Hao Tsai; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US20190355680A1

## CPC

- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}
- H01Q 9/0457: {electromagnetically coupled to the feed line}
- H01Q 21/0087: {Apparatus or processes specially adapted for manufacturing antenna arrays (manufacturing waveguides H01P11/00)}
- H01Q 21/062: {using dipole aerials; (H01Q21/067, H01Q21/068 take precedence)}
- H01Q 21/065: {Patch antenna array}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 44/248: {for antennas}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

## Claims

### Claim 1

A semiconductor device comprising:
redistribution structures connected to external connections;
a first semiconductor device connected to the redistribution structures;
an antenna substrate located on an opposite side of the first semiconductor device from the redistribution structures; and
electrical connections separate from the first semiconductor device, the first semiconductor device being electrically connected to the antenna substrate through the redistribution structures and the electrical connections.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising an antenna structure located within the redistribution structures.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising an antenna structure located within the electrical connections.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the antenna substrate comprises a plurality of antenna structures.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a thermal via extending through the antenna substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the electrical connections are through substrate vias.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor device is a radio frequency chip.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
forming a redistribution structure over a carrier wafer;
attaching a first semiconductor device to the redistribution structure;
electrically connecting an antenna substrate to the redistribution structure, wherein the first semiconductor device is located between the antenna substrate and the redistribution structure; and
removing the carrier wafer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the forming the redistribution structure comprises forming an antenna simultaneously within the redistribution structure.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first semiconductor device is a radio frequency chip.

### Claim 11 (depends on 8)

The method of claim 8, wherein the electrically connecting the antenna substrate comprises electrically connecting a first antenna layer and a second antenna layer to the redistribution structure, wherein the first antenna layer is oriented at a right angle to the second antenna layer.

### Claim 12 (depends on 8)

The method of claim 8, further comprising encapsulating the first semiconductor device after the electrically connecting the antenna substrate to the redistribution structure.

### Claim 13 (depends on 8)

The method of claim 8, wherein the electrically connecting the antenna substrate further comprises:
forming electrical connections separate from the first semiconductor device; and
bonding the antenna substrate to the electrical connections.

### Claim 14 (depends on 13)

The method of claim 13, wherein the forming the electrical connections comprises forming an antenna simultaneously with the electrical connections.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
forming through substrate vias over a polymer layer;
attaching a first semiconductor device to the polymer layer;
encapsulating the through substrate vias and the first semiconductor device with an encapsulant;
planarizing the encapsulant until the first semiconductor device, the encapsulant, and the through substrate vias are planar with each other;
forming a redistribution structure over the encapsulant, the through substrate vias, and the first semiconductor device;
patterning the polymer layer after the forming the redistribution structure; and
bonding an antenna substrate to the through substrate vias through the polymer layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming the redistribution structure comprises forming an antenna simultaneously with the redistribution structure.

### Claim 17 (depends on 15)

The method of claim 15, wherein the forming the through substrate vias forms an antenna simultaneously with the through substrate vias.

### Claim 18 (depends on 15)

The method of claim 15, wherein the first semiconductor device is a radio frequency chip.

### Claim 19 (depends on 15)

The method of claim 15, wherein the antenna substrate includes a plurality of upper antenna layers, one of the plurality of upper antenna layers being oriented in a different direction from another of the plurality of upper antenna layers.

### Claim 20 (depends on 15)

The method of claim 15, further comprising applying an underfill material between the antenna substrate and the polymer layer.