# US 2019/0355679 A1 · Package structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355679 A1 - Document ID: US20190355679A1 - Status: Published application - Kind: A1 - Application number: 15/980,764 - Filed: 2018-05-16 - Published: 2019-11-21 - Earliest claimed: 2018-05-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Kai-Chiang Wu; Han-Ping Pu; Yen-Ping Wang - Web page: https://patentgrep.com/patent/US20190355679A1 ## CPC - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/614: {the multiple chips being integrally enclosed} - H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package} - H10P 72/74: {using temporarily an auxiliary support} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/01: Manufacture or treatment - H10W 74/014: {using batch processing} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 44/209: {Vertical interconnections, e.g. vias} - H10W 44/248: {for antennas} - H10W 46/101: {characterised by the type of information, e.g. logos or symbols} - H10W 46/301: {for alignment} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. ## Claims ### Claim 1 A package structure, comprising: a chip package, comprising at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die; and an antenna package, located on and electrically coupled to the chip package, wherein the antenna package comprises: metallic patterns, embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. ### Claim 2 (depends on 1) The package structure of claim 1, wherein the second surface of each of the metallic patterns is accessibly revealed by the third surface of the second insulating encapsulation. ### Claim 3 (depends on 1) The package structure of claim 1, further comprising: a connecting film, located on a fourth surface of the second insulating encapsulation, wherein the third surface is opposite to the fourth surface, and the connecting film is located between the chip package and the antenna package. ### Claim 4 (depends on 3) The package structure of claim 3, wherein two opposite sides of the connecting film physically contact the second insulating encapsulation and the chip package, respectively. ### Claim 5 (depends on 1) The package structure of claim 1, wherein the chip package further comprises: a first redistribution circuit structure, located between the antenna package and the first insulating encapsulation and electrically connected to the at least one semiconductor die, wherein the first redistribution circuit structure comprises at least one alignment mark. ### Claim 6 (depends on 5) The package structure of claim 5, wherein the at least one alignment mark comprises a predetermined pattern of a solid metal plate having at least one slit. ### Claim 7 (depends on 6) The package structure of claim 6, wherein a shape of the at least one slit comprise a L-shape, a cross-shape, a circular-shape, a triangular-shape, a rectangular shape, or combinations thereof. ### Claim 8 (depends on 5) The package structure of claim 5, wherein the chip package further comprises: a second redistribution circuit structure, located on the first insulating encapsulation and electrically connected to the at least one semiconductor die, wherein the first insulating encapsulation is located between the antenna package and the second redistribution circuit; through vias, penetrating the first insulating encapsulation and connecting to the first redistribution circuit structure and the second redistribution circuit structure; and conductive elements, located on and electrically connected to the second redistribution circuit structure, wherein the second redistribution circuit structure is located between the first insulating encapsulation and the conductive elements. ### Claim 9 (depends on 1) The package structure of claim 1, wherein a sidewall of the antenna package is aligned with a sidewall of the chip package along a stacking direction of the antenna package and the chip package. ### Claim 10 (depends on 1) The package structure of claim 1, wherein a sidewall of the antenna package is distant from a sidewall of the chip package on a direction perpendicular to a stacking direction of the antenna package and the chip package. ### Claim 11 A package structure, comprising: a first redistribution circuit structure; at least one semiconductor die, located on and electrically connected to the first redistribution circuit structure; a first insulating encapsulation, encapsulating the at least one semiconductor die; metallic patterns, located on and electrically coupled to the first redistribution circuit structure; and a second insulating encapsulation, encapsulating the metallic patterns, wherein the first redistribution circuit structure is located between the first insulating encapsulation and the second insulating encapsulation, wherein a sidewall of each of the metallic patterns is wrapped by the second insulating encapsulation, and a surface of each of the metallic patterns is exposed by a first side of the second insulating encapsulation. ### Claim 12 (depends on 11) The package structure of claim 11, further comprising: a third insulating encapsulation, located between the second insulating encapsulation and the first redistribution circuit structure, wherein a second side of the second insulating encapsulation is covered by the third insulating encapsulation. ### Claim 13 (depends on 12) The package structure of claim 12, wherein a third surface of the second insulating encapsulation is covered by the third insulating encapsulation, and the third surface of the second insulating encapsulation connects the first side and the second side. ### Claim 14 (depends on 11) The package structure of claim 11, wherein the first redistribution circuit structure comprises at least one alignment mark having a solid metal plate with at least one slit, and a shape of the at least one slit comprise a L-shape, a cross-shape, a circular-shape, a triangular-shape, a rectangular-shape, or combinations thereof. ### Claim 15 (depends on 11) The package structure of claim 11, further comprising: through vias, penetrating the first insulating encapsulation and connecting to the first redistribution circuit structure and the second redistribution circuit structure; and conductive elements, located on and electrically connected to the second redistribution circuit structure, wherein the second redistribution circuit structure is located between the first insulating encapsulation and the conductive elements. ### Claim 16 (depends on 11) The package structure of claim 11, wherein a sidewall of the antenna package is aligned with a sidewall of the chip package along a stacking direction of the antenna package and the chip package. ### Claim 17 (depends on 11) The package structure of claim 11, wherein a sidewall of the antenna package is distant from a sidewall of the chip package on a direction perpendicular to a stacking direction of the antenna package and the chip package. ### Claim 18 A method of manufacturing a package structure, comprising: forming an antenna package, comprising: providing an insulating material layer; forming metallic patterns on the insulating material layer; encapsulating metallic patterns in a first insulating encapsulation; and performing a dicing process to form the antenna package, wherein a sidewall of each of the metallic patterns is covered by the first insulating encapsulation; forming a first redistribution circuit structure; disposing at least one semiconductor die on the first redistribution circuit structure, wherein the at least one semiconductor die is electrically connected to the first redistribution circuit structure; encapsulating the at least one semiconductor die in a second insulating encapsulation; and disposing the antenna package on the first redistribution circuit structure, wherein the first redistribution circuit structure is electrically coupled to the antenna package and located between the at least one semiconductor die and the antenna package. ### Claim 19 (depends on 18) The method of claim 18, wherein forming the antenna package further comprises encapsulating the first insulating encapsulation in a third insulating encapsulation prior to performing the dicing process, and wherein the third insulating encapsulation is located between the first insulating encapsulation and the second insulating encapsulation. ### Claim 20 (depends on 18) The method of claim 18, wherein forming the first redistribution circuit structure further comprises forming at least one alignment mark having a solid metal plate with at least one slit, and a shape of the at least one slit comprise a L-shape, a cross-shape, a circular-shape, a triangular-shape, a rectangular-shape, or combinations thereof.