# US 2019/0355672 A1 · Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same

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- Number: US 2019/0355672 A1
- Document ID: US20190355672A1
- Status: Published application
- Kind: A1
- Application number: 15/982,188
- Filed: 2018-05-17
- Published: 2019-11-21
- Earliest claimed: 2018-05-17
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Takahito FUJITA; Kiyokazu SHISHIDO; Hiroyuki OGAWA
- Web page: https://patentgrep.com/patent/US20190355672A1

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/0372: {comprising multiple barrier, adhesion or liner layers}
- H10W 20/0698: {Local interconnections}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor device located on a semiconductor substrate;
a planarization dielectric layer located on the semiconductor device and over the semiconductor substrate;
a silicon nitride diffusion barrier layer located on the planarization dielectric layer;
a via level dielectric layer overlying the silicon nitride diffusion barrier layer; and
a composite contact via structure in contact with a component of the semiconductor device and extending through the planarization dielectric layer, the silicon nitride diffusion barrier layer, and the via level dielectric layer, wherein the composite contact via structure comprises, from bottom to top:
a lower metallic via structure in contact with the component of the semiconductor device;
a titanium diffusion barrier structure in contact with a top surface of the lower metallic via structure and contacting the silicon nitride diffusion barrier layer; and
an upper metallic via structure overlying, and electrically contacts the titanium diffusion barrier structure and extending through the via level dielectric layer,
wherein:
a top surface of the lower metallic via structure contacts the titanium diffusion barrier structure; and
the top surface of the lower metallic via structure is located between a horizontal plane including a top surface of the silicon nitride diffusion barrier layer and a horizontal plane including a bottom surface of the silicon nitride diffusion barrier layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor device is a field effect transistor, and the component of the semiconductor device is selected a gate electrode, a source region or a drain region of the field effect transistor.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, further comprising a three-dimensional NAND memory array located over the composite contact via structure and over the field effect transistor, wherein the field effect transistor is a part of a driver circuit of the three-dimensional NAND memory array.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein:
the lower metallic via structure comprises a lower metal nitride liner in contact with the component of the semiconductor device and a lower metal fill portion consisting essentially of at least one first metal element and embedded in the lower metal nitride liner and contacting a bottom surface of the titanium diffusion barrier structure; and
the upper metallic via structure comprises an upper metal nitride liner and an upper metal fill portion consisting essentially of at least one second metal element and embedded in the upper metal nitride liner.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a sidewall of the titanium diffusion barrier structure and a sidewall of the upper metallic via structure contact only dielectric surfaces and do not contact any conductive surface.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein:
an upper portion of a sidewall of the lower metallic via structure contacts a lower portion of a sidewall of the silicon nitride diffusion barrier layer; and
a top surface of the composite contact via structure is within a same horizontal plane as a top surface of the via level dielectric layer.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein a top surface of the titanium diffusion barrier structure is located below a horizontal plane including a top surface of the silicon nitride barrier layer.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein a sidewall of the titanium diffusion barrier structure contacts a sidewall of the silicon nitride diffusion barrier layer and is vertically coincident with an outer sidewall of the upper metallic via structure, and with an outer sidewall of the lower metallic via structure.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein:
a sidewall of the titanium diffusion barrier structure contacts a sidewall of the silicon nitride diffusion barrier layer and is vertically coincident with an outer sidewall of the upper metallic via structure; and
the titanium diffusion barrier structure has a greater maximum lateral dimension than a maximum lateral dimension of the lower metallic via structure.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the upper metallic via structure has a lesser maximum lateral dimension than a maximum lateral dimension of the titanium diffusion barrier structure.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, further comprising an intermediate dielectric material layer located between the silicon nitride barrier layer and the via level dielectric layer, wherein the titanium diffusion barrier structure has a top surface that is coplanar with a top surface of the intermediate dielectric material layer.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, further comprising a metallic pad portion comprising at least one metal and contacting a top surface of the titanium diffusion barrier structure and a bottom surface of the upper metallic via structure.

### Claim at position 13

-20. (canceled)

### Claim 21 (depends on 1)

The semiconductor structure of claim 1, wherein the titanium diffusion barrier structure consists essentially of titanium.

### Claim 22 (depends on 1)

The semiconductor structure of claim 1, wherein a top surface of the lower metallic via structure and a horizontal surface of the silicon nitride diffusion barrier layer contact a bottom surface of the titanium diffusion barrier structure.

### Claim 23 (depends on 1)

The semiconductor structure of claim 1, wherein an entirety of an interface between the titanium diffusion barrier structure and the silicon nitride diffusion barrier layer is vertically coincident with an entirety of an interface between the upper metallic via structure and the via level dielectric layer.

### Claim 24 (depends on 23)

The semiconductor structure of claim 23, wherein an entirety of an interface between the upper metallic via structure and the silicon nitride diffusion barrier layer is vertically coincident with the entirety of the interface between the upper metallic via structure and the via level dielectric layer

### Claim 25 (depends on 23)

The semiconductor structure of claim 23, wherein an entirety of an interface between the lower metallic via structure and the planarization dielectric layer is vertically coincident with the entirety of the interface between the titanium diffusion barrier structure and the silicon nitride diffusion barrier layer.

### Claim 26 (depends on 1)

The semiconductor structure of claim 1, wherein:
the upper metallic via structure has a same lateral dimension irrespective of a distance from the substrate between an interface with the titanium diffusion barrier structure and a horizontal plane including a top surface of the via level dielectric layer; and
an entirety of a sidewall of the upper metallic via structure is vertically coincident with an entirety of a sidewall of the titanium diffusion barrier structure.

### Claim 27 (depends on 1)

The semiconductor structure of claim 1, wherein:
an entirety of a bottom surface of the titanium diffusion barrier structure contacts an entirety of a top surface of the lower metallic via structure;
an entirety of a sidewall of the titanium diffusion barrier structure contacts a sidewall of the silicon nitride diffusion barrier layer; and
an entirety of a top surface of the titanium diffusion barrier structure contacts an entirety of a bottom surface of the lower metallic via structure.