# US 2019/0355668 A1 · Selective cvd alignment-mark topography assist for non-volatile memory

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- Number: US 2019/0355668 A1
- Document ID: US20190355668A1
- Status: Published application
- Kind: A1
- Application number: 15/983,689
- Filed: 2018-05-18
- Published: 2019-11-21
- Earliest claimed: 2018-05-18
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Michael Rizzolo; Chih-Chao Yang; Lawrence A. Clevenger; Benjamin D. Briggs
- Web page: https://patentgrep.com/patent/US20190355668A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
recessing a device pad to below a top surface of an interconnect layer;
depositing a cap in the recess over the device pad;
forming a topography assist layer over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the cap of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap;
depositing device layers conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer; and
aligning the device pad according to the topographical feature.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the cap is formed from a metal nitride.

### Claim 3 (depends on 2)

The method as recited in claim 2, wherein the metal nitride includes tantalum nitride.

### Claim 4 (depends on 1)

The method as recited in claim 1, further including forming the device pad in a dielectric layer of the interconnect layer in a device region; and
forming the at least one alignment mark in the dielectric layer of the interconnect layer in an alignment region.

### Claim 5 (depends on 4)

The method as recited in claim 4, further including forming a block mask over the alignment region to recess the device pad.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein each of the device pad and the at least one alignment mark are formed of copper.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein the selective deposition process includes chemical vapor deposition of a selective metal.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein the selective deposition process includes electroless plating of a selective metal.

### Claim 9 (depends on 1)

The method as recited in claim 1, further including forming a memory device in an aligned area over the device pad by removing the device layers outside of the aligned area.

### Claim 10 (depends on 1)

The method as recited in claim 1, further including:
forming vias down to the memory device through a dielectric fill over the interconnect layer and down to the alignment mark through the dielectric fill and the topographic assist layer;
forming vias up to each of the device pad and the alignment k through a substrate and the interconnect layer; and
filling each of the vias with a conductive material to form contacts.

### Claim 11

A method for forming a semiconductor device, the method comprising:
forming pads in a dielectric layer on a substrate to form an interconnect layer with at least an alignment region and a device region;
patterning a block mask over the alignment region;
recessing a pad in the device region to below a top surface of an interconnect layer;
depositing a metal nitride in the recess over the device pad;
forming a topography assist layer over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad;
depositing device layers conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer; and
aligning the device region according to the topographical feature.

### Claim 12 (depends on 11)

The method as recited in claim 11, wherein each of the device pad and the at least one alignment mark are formed of copper.

### Claim 13 (depends on 11)

The method as recited in claim 11, wherein the selective deposition process includes chemical vapor deposition of a selective metal.

### Claim 14 (depends on 11)

The method as recited in claim 11, wherein the selective deposition process includes electroless plating of a selective metal.

### Claim 15 (depends on 11)

The method as recited in claim 11, further including:
forming vias down to the memory device through a dielectric fill over the interconnect layer and down to the alignment mark through the dielectric fill and the topographic assist layer;
forming vias up to each of the device pad and the alignment mark through the substrate and the interconnect layer; and
filling each of the vias with a conductive material to form contacts.

### Claim 16

A semiconductor device, comprising:
a dielectric material disposed on a substrate having a landing pad in a device region and a landing pad in an alignment region disposed within the dielectric material;
a cap disposed in an upper portion of the landing pad in the device region;
a topography assist layer disposed on the landing pad in the alignment region, the topography assist layer having an upper surface that is at a different level than upper surface of the cap relative to the substrate; and
a memory device embedded in the dielectric material and aligned over the cap.

### Claim 17 (depends on 16)

The semiconductor device as recited in claim 16, wherein each of the device pad and the at least one alignment mark are formed of copper.

### Claim 18 (depends on 16)

The semiconductor device as recited in claim 16, wherein the topography assist layer includes metal that is deposited on the at least one alignment mark selective to the cap.

### Claim 19 (depends on 16)

The semiconductor device as recited in claim 16, wherein the cap includes a metal nitride barrier.

### Claim 20 (depends on 16)

The semiconductor device as recited in claim 16, further including:
front side contacts aligned with each of the memory device and the landing pad in the alignment region; and
middle of line contacts aligned with each of the landing pad in the device region and the landing pad in the alignment region.