# US 2019/0355666 A1 · Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355666 A1 - Document ID: US20190355666A1 - Status: Published application - Kind: A1 - Application number: 16/510,295 - Filed: 2019-07-12 - Published: 2019-11-21 - Earliest claimed: 2018-05-09 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Eric J. Li; Timothy A. Gosselin; Yoshihiro Tomita; Shawna M. Liff; Amram Eitan; Mark Saltas - Web page: https://patentgrep.com/patent/US20190355666A1 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/68: Shapes or dispositions thereof - H10W 72/00: Interconnections or connectors in packages - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/014: {using batch processing} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 70/63: Vias, e.g. via plugs - H10W 70/682: {comprising holes having chips therein} - H10W 70/685: comprising multiple insulating layers - H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates} - H10W 72/01215: {forming coatings} - H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing} - H10W 72/01304: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07252: {changes in structures or sizes} - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/07352: {changes in structures or sizes} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/228: {Multiple bumps having different structures} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/321: {Structures or relative sizes of die-attach connectors} - H10W 72/551: {Materials of bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge. ## Claims ### Claim 1 A microelectronic structure, comprising: a reconstituted wafer comprising a first microelectronic device and a second microelectronic device, wherein the first microelectronic device and the second microelectronic device each include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; a microelectronic bridge attached to the reconstituted wafer, wherein the microelectronic bridge is attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; and a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity. ### Claim 2 (depends on 1) The microelectronic structure of claim 1, wherein the reconstituted wafer comprises an encapsulant material disposed between at least one side of the first microelectronic device and at least one side of the second microelectronic device. ### Claim 3 (depends on 1) The microelectronic structure of claim 1, wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device. ### Claim 4 (depends on 3) The microelectronic structure of claim 3, wherein the microelectronic bridge includes a plurality of conductive routes therein. ### Claim 5 (depends on 3) The microelectronic structure of claim 3, wherein the microelectronic bridge includes at least one microelectronic device embedded therein. ### Claim 6 A microelectronic structure comprising: a first microelectronic device, wherein the first microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; a second microelectronic device, wherein the second microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; a microelectronic bridge attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity; a first underfill material encapsulating the high density interconnect structures of the first microelectronic device and encapsulating the high density interconnect structures of the second microelectronic device; and an second underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within the microelectronic substrate cavity. ### Claim 7 (depends on 6) The microelectronic structure of claim 6, wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device. ### Claim 8 (depends on 7) The microelectronic structure of claim 7, wherein the microelectronic bridge includes a plurality of conductive routes therein. ### Claim 9 (depends on 7) The microelectronic structure of claim 7, wherein the microelectronic bridge includes at least one microelectronic device embedded therein. ### Claim 10 (depends on 6) The microelectronic structure of claim 6, further comprising a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. ### Claim 11 (depends on 10) The microelectronic structure of claim 10, wherein the reconstituted wafer includes an encapsulant material between at least one side of the first microelectronic device and at least one side of the second microelectronic device. ### Claim 12 A computing device, comprising: a board; and a microelectronic structure attached to the board, wherein the microelectronic structure comprises: a reconstituted wafer including a first microelectronic device and a second microelectronic device, wherein the first microelectronic device and the second microelectronic device each include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; a microelectronic bridge attached to the reconstituted wafer, wherein the microelectronic bridge is attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; and a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity. ### Claim 13 (depends on 12) The computing device of claim 12, wherein the reconstituted wafer comprises an encapsulant material disposed between at least one side of the first microelectronic device and at least one side of the second microelectronic device. ### Claim 14 (depends on 12) The computing device of claim 12, wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device. ### Claim 15 (depends on 14) The computing device of claim 14, wherein the microelectronic bridge includes a plurality of conductive routes therein. ### Claim 16 (depends on 14) The computing device of claim 14, wherein the microelectronic bridge includes at least one microelectronic device embedded therein. ### Claim 17 A computing device, comprising: a board; and a microelectronic structure attached to the board, wherein the microelectronic structure comprises: a first microelectronic device, wherein the first microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; a second microelectronic device, wherein the second microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; a microelectronic bridge attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity; a first underfill material encapsulating the high density interconnect structures of the first microelectronic device and encapsulating the high density interconnect structures of the second microelectronic device; and an second underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within the microelectronic substrate cavity. ### Claim 18 (depends on 17) The computing device of claim 17, wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device. ### Claim 19 (depends on 18) The computing device of claim 18, wherein the microelectronic bridge includes a plurality of conductive routes therein. ### Claim 20 (depends on 18) The computing device of claim 18, wherein the microelectronic bridge includes at least one microelectronic device embedded therein. ### Claim 21 (depends on 17) The computing device of claim 17, further comprising a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. ### Claim 22 (depends on 21) The computing device of claim 21, wherein the reconstituted wafer includes an encapsulant material between at least one side of the first microelectronic device and at least one side of the second microelectronic device.