# US 2019/0355663 A1 · Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same

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- Number: US 2019/0355663 A1
- Document ID: US20190355663A1
- Status: Published application
- Kind: A1
- Application number: 15/982,215
- Filed: 2018-05-17
- Published: 2019-11-21
- Earliest claimed: 2018-05-17
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Masatoshi NISHIKAWA; Akio NISHIDA; Murshed CHOWDHURY; Takahito FUJITA; Kiyokazu SHISHIDO; Hiroyuki OGAWA
- Web page: https://patentgrep.com/patent/US20190355663A1

## CPC

- H10W 20/0698: {Local interconnections}
- H10W 20/48: Insulating materials thereof
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/033: {in openings in dielectrics}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/0372: {comprising multiple barrier, adhesion or liner layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
semiconductor devices;
a silicon nitride diffusion barrier layer overlying the semiconductor devices; and
an interconnect structure extending through the silicon nitride diffusion barrier layer, wherein the interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein:
the semiconductor devices are located on a semiconductor substrate;
a first dielectric material layer overlies a portion of the semiconductor devices and embeds at least portions of first metal interconnect structures;
the silicon nitride diffusion barrier layer overlies the first dielectric material layer and includes a set of openings therein;
the titanium diffusion barrier structure comprises a set of titanium plates filling the set of openings, wherein the silicon nitride diffusion barrier layer and the set of titanium plates complimentarily provide a continuous structure extending over the semiconductor substrate, and wherein a conductive structure embedded in the first dielectric material layer contacts a titanium plate among the set of titanium plates, and the conductive structure comprises a component of the semiconductor devices or one of the first metal interconnect structures; and
the interconnect structure comprises second metal interconnect structures embedded within a second dielectric material layer overlying the silicon nitride diffusion barrier layer, wherein one of the second metal interconnect structures contacts a top surface of the titanium plate among the set of titanium plates.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein:
the set of titanium plates has a first uniform thickness;
the silicon nitride diffusion barrier layer has the first uniform thickness.
a planar top surface of each titanium plate within the set of titanium plates is within a horizontal plane containing a top surface of the silicon nitride diffusion barrier layer; and
a planar bottom surface of each titanium plate within the set of titanium plates is with another horizontal plane containing a bottom surface of the silicon nitride diffusion barrier layer.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein each titanium plate among the set of titanium plates consists essentially of titanium.

### Claim 5 (depends on 2)

The semiconductor structure of claim 2, wherein:
a portion of a bottom surface of a titanium plate among the set of titanium plates directly contacts the first dielectric material layer;
a portion of a top surface of the titanium plate among the set of titanium plates directly contacts the second dielectric material layer; and
an entire periphery of a bottom surface of the one of the second metal interconnect structures contacts another portion of the top surface of the titanium plate.

### Claim 6 (depends on 2)

The semiconductor structure of claim 2, wherein:
the conductive structure comprises one of the first metal interconnect structures;
a bottom surface of the first dielectric material layer is more distal from the semiconductor substrate than a topmost surface of the semiconductor devices is from the semiconductor substrate; and
the one of the second metal interconnect structures comprises a via structure.

### Claim 7 (depends on 2)

The semiconductor structure of claim 2, wherein:
the conductive structure comprises a gate electrode of a field effect transistor;
the first dielectric material layer comprises a material selected from an undoped silicate glass, a doped silicate glass, and an organosilicate glass, and laterally surrounds the gate electrode; and
the one of the second metal interconnect structures comprises a via structure.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the silicon nitride diffusion barrier layer contacts a planar top surface of a dielectric gate spacer that laterally surrounds the gate electrode.

### Claim 9 (depends on 2)

The semiconductor structure of claim 2, further comprising:
an additional silicon nitride diffusion barrier layer overlying the second dielectric material layer and including a set of additional openings therein;
a set of additional titanium plates filling the set of additional openings, wherein the additional silicon nitride diffusion barrier layer and the set of additional titanium plates complimentarily provide an additional continuous hydrogen diffusion barrier structure extending over the continuous hydrogen diffusion barrier structure, and another one of the second metal interconnect structures contacts an additional titanium plate among the set of additional titanium plates; and
third metal interconnect structures embedded within a third dielectric material layer overlying the additional silicon nitride diffusion barrier layer, wherein one of the third metal interconnect structures contacts a top surface of the additional titanium plate among the set of additional titanium plates.

### Claim 10 (depends on 2)

The semiconductor structure of claim 2, further comprising a three-dimensional NAND memory array located over the second dielectric material layer, wherein the semiconductor devices comprise a driver circuit of the three-dimensional NAND memory array.

### Claim 11

A method of forming a semiconductor structure, comprising:
forming semiconductor devices on a semiconductor substrate;
forming a first dielectric material layer over a portion of the semiconductor devices, wherein a conductive structure selected from a component of the semiconductor devices and a first metal interconnect structure is laterally surrounded by the first dielectric material layer;
forming a silicon nitride diffusion barrier layer over the first dielectric material layer;
forming a set of openings through the silicon nitride diffusion barrier layer;
forming a set of titanium plates in the set of openings, wherein the silicon nitride diffusion barrier layer and the set of titanium plates complimentarily provide a continuous hydrogen diffusion barrier structure extending over the semiconductor substrate, and a titanium plate among the set of titanium plates is formed directly on a top surface the conductive structure; and
forming second metal interconnect structures embedded within a second dielectric material layer over the silicon nitride diffusion barrier layer, wherein one of the second metal interconnect structures is formed on a top surface of the titanium plate among the set of titanium plates.

### Claim 12 (depends on 11)

The method of claim 11, wherein the set of titanium plates is formed by:
forming a titanium layer that continuously extends over the silicon nitride diffusion barrier layer and filling the set of openings by depositing titanium; and
removing portions of deposited titanium from above a horizontal plane including a top surface of the silicon nitride diffusion barrier layer, wherein remaining portions of the deposited titanium layer constitute the set of titanium plates.

### Claim 13 (depends on 12)

The method of claim 12, wherein a set of openings through the silicon nitride diffusion barrier layer is formed by:
forming an etch mask layer including openings therethrough over the silicon nitride diffusion barrier layer; and
etching uncovered portions of the silicon nitride diffusion barrier layer selective to the first dielectric material layer and the conductive structure.

### Claim 14 (depends on 11)

The method of claim 11, wherein each titanium plate among the set of titanium plates consists essentially of titanium.

### Claim 15 (depends on 11)

The method of claim 11, wherein:
the titanium plate is formed directly on a top surface of the first dielectric material layer;
the second dielectric material layer is formed directly on a portion of a top surface of the titanium plate; and
the second metal interconnect structures are formed by forming via cavities through the second dielectric material layer and filling the via cavities with at least one conductive material that is deposited directly on top surfaces of the set of titanium plates.

### Claim 16 (depends on 11)

The method of claim 11, wherein:
the conductive structure comprises one of the first metal interconnect structures;
the method further comprises forming a planarization dielectric layer including a top surface located at, or above, a topmost surface of the semiconductor devices;
the first dielectric material layer is formed over the planarization dielectric layer; and
the one of the second metal interconnect structures comprises a via structure.

### Claim 17 (depends on 11)

The method of claim 11, wherein:
the conductive structure comprises a gate electrode of a field effect transistor;
the first dielectric material layer comprises a planarization dielectric layer having a top surface located at a topmost surface of the semiconductor devices; and
the one of the second metal interconnect structures comprises a via structure.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
depositing a planarization dielectric material over the semiconductor devices; and
removing the planarization dielectric material employing a planarization process above a horizontal plane including a top surface of the gate electrode,
wherein:
a remaining portion of the planarization dielectric material comprises the planarization dielectric layer; and
the silicon nitride diffusion barrier layer is formed on a planar top surface of a dielectric gate spacer that laterally surrounds the gate electrode.

### Claim 19 (depends on 11)

The method of claim 11, further comprising:
forming an additional silicon nitride diffusion barrier layer over the second dielectric material layer;
forming a set of additional openings through the additional silicon nitride diffusion barrier layer;
forming a set of additional titanium plates in the set of additional openings, wherein the additional silicon nitride diffusion barrier layer and the set of additional titanium plates complimentarily provide an additional continuous hydrogen diffusion barrier structure extending over the continuous hydrogen diffusion barrier structure, and another one of the second metal interconnect structures contacts an additional titanium plate among the set of additional titanium plates; and
forming third metal interconnect structures embedded within a third dielectric material layer over the additional silicon nitride diffusion barrier layer, wherein one of the third metal interconnect structures is formed on a top surface of the additional titanium plate among the set of additional titanium plates.

### Claim 20 (depends on 11)

The method of claim 11, further comprising forming a three-dimensional NAND memory array over the second dielectric material layer, wherein the semiconductor devices comprise a driver circuit of the three-dimensional NAND memory array.