# US 2019/0355662 A1 · Semiconductor device and method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0355662 A1
- Document ID: US20190355662A1
- Status: Published application
- Kind: A1
- Application number: 16/526,018
- Filed: 2019-07-30
- Published: 2019-11-21
- Earliest claimed: 2012-12-13
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Takeshi KAWAMURA
- Web page: https://patentgrep.com/patent/US20190355662A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10P 50/283: {by chemical means}
- H10P 74/238: {comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement}
- H10P 95/064: {the removal being chemical etching}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

## Claims

### Claim 1

A semiconductor device comprising:
a first interlayer insulating film formed on a semiconductor substrate;
a first plug formed inside the first interlayer insulating film;
a second interlayer insulating film formed on the first interlayer insulating film and having a dielectric constant lower than a dielectric constant of silicon oxide; and
a first buried wiring formed inside the second interlayer insulating film and connected to the first plug,
an upper surface of the first plug being formed at a position higher than an upper surface of the first interlayer insulating film, and
a lower surface of the first buried wiring being formed at a position lower than the upper surface of the first plug.