# US 2019/0355661 A1 · Beol embedded high density vertical resistor structure

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- Number: US 2019/0355661 A1
- Document ID: US20190355661A1
- Status: Published application
- Kind: A1
- Application number: 16/531,846
- Filed: 2019-08-05
- Published: 2019-11-21
- Earliest claimed: 2017-12-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alexander Reznicek; Oscar van der Straten; Praneet Adusumilli
- Web page: https://patentgrep.com/patent/US20190355661A1

## CPC

- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- H10D 1/47: Resistors having no potential barriers
- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10D 84/209: {of only resistors}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
forming a lower interconnect level that includes at least one first metal-containing structure embedded in a first interconnect dielectric material layer;
forming a plurality of spaced apart mandrel structures above the lower interconnect level;
forming a resistor material pillar on opposing sidewall surfaces of each of the mandrel structures;
removing each mandrel structure;
forming a dielectric material layer between each resistor material pillar; and
forming an upper interconnect level that includes at least one second metal-containing structure located in a second interconnect dielectric material layer, wherein at least one of the resistor material pillars contacts both the first and second metal-containing structures.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the resistor material pillar comprises:
depositing a resistor material layer; and
performing a spacer etch.

### Claim 3 (depends on 1)

The method of claim 1, wherein the resistor material pillar composed of a ceramic conductor material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the ceramic conductor material comprises a metal nitride, a metal oxide or a combination thereof.

### Claim 5 (depends on 4)

The method of claim 4, wherein the metal nitride comprises tantalum nitride (TaN), niobium nitride (NbN), vanadium nitride (VN), titanium nitride (TiN) or tungsten nitride (WN).

### Claim 6 (depends on 4)

The method of claim 4, wherein the metal oxide comprises ruthenium oxide (RuO), osmium oxide (OsO), rhodium oxide (RhO) or iridium oxide (IrO).

### Claim 7 (depends on 1)

The method of claim 1, wherein the resistor material pillar comprises TaN having a resistivity from 200 μΩcm to 10,000 μΩcm.

### Claim 8 (depends on 1)

The method of claim 1, wherein the resistor material pillar comprises RuO having a resistivity from 20 μΩcm to 200 μΩcm.

### Claim 9 (depends on 1)

The method of claim 1, wherein each resistor material pillar has a topmost surface that is coplanar with a topmost surface of each mandrel structure.

### Claim 10 (depends on 1)

The method of claim 1, further comprising forming a capping layer on the lower interconnect layer prior to forming the plurality of mandrel structures.

### Claim 11 (depends on 10)

The method of claim 10, further comprising transferring a pattern of the mandrel structures into the capping layer prior to forming the resistor material pillar.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first interconnect dielectric material layer, the dielectric material layer and the second interconnect dielectric material layer comprise a same dielectric material.

### Claim 13 (depends on 1)

The method of claim 1, wherein at least one of the resistor material pillars contacts has a topmost surface that contacts directly a surface of the second interconnect dielectric material layer.

### Claim 14 (depends on 1)

The method of claim 1, wherein at least one of the resistor material pillars contacts has a bottommost surface that contacts directly a surface of the second interconnect dielectric material layer.

### Claim 15 (depends on 1)

The method of claim 1, wherein a diffusion barrier liner is formed that separates a topmost surface of the at least one of resistor material pillar that contacts both the first and second metal-containing structures from a bottommost surface of the second metal-containing structure.

### Claim 16 (depends on 1)

The method of claim 1, wherein the mandrel structure is composed of silicon nitride or amorphous silicon.

### Claim 17 (depends on 1)

The method of claim 1, wherein each of the resistor material pillars has a height that is greater than a width.

### Claim 18 (depends on 17)

The method of claim 17, wherein the height of each of the resistor material pillars is from 40 nm to 300 nm, and the width of each of the resistor material pillars from 2 nm to 100.

### Claim 19 (depends on 2)

The method of claim 2, wherein the spacer etch removes horizontal portions of the resistor material layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the spacer etch comprises reactive ion etching.