# US 2019/0355648 A1 · Semiconductor power device including ring frame for thermal impedance reduction

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- Number: US 2019/0355648 A1
- Document ID: US20190355648A1
- Status: Published application
- Kind: A1
- Application number: 15/984,271
- Filed: 2018-05-18
- Published: 2019-11-21
- Earliest claimed: 2018-05-18
- Assignees: Integra Technologies, Inc.
- Applicants: Integra Technologies, Inc.
- Inventors: William Veitschegger
- Web page: https://patentgrep.com/patent/US20190355648A1

## CPC

- H10W 40/10: Arrangements for heating
- H10W 70/465: {Bumps or wires}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/254: {Diamond}
- H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 40/60: Securing means for detachable heating or cooling arrangements, e.g. clamps
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 44/00: Electrical arrangements for controlling or matching impedance
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40)
- H10W 90/00: Package configurations
- H10D 30/471: {High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]}
- H10W 70/413: {Insulating or insulated substrates serving as die pads (H10W70/468 takes precedence)}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor power device including a base plate, a ring frame disposed over the base plate, a semiconductor power die disposed on the base plate and surrounded by the ring frame, an input lead by way the semiconductor power die receives an input signal, wherein the input lead is disposed over a first portion of the ring frame, and an output lead by way an output signal generated by the semiconductor power die is sent to another device, wherein the output lead is disposed over a second portion of the ring frame. The ring frame may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The ring frame produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.

## Claims

### Claim 1

A semiconductor power device, comprising:
a base plate;
a ring frame disposed on the base plate;
an input lead disposed on the ring frame;
an output lead disposed on the ring frame; and
a semiconductor power die disposed on the base plate and surrounded by the ring frame, wherein the semiconductor power die is configured to receive an input signal from the input lead and generate an output signal at the output lead.

### Claim 2 (depends on 1)

The semiconductor power device of claim 1, wherein the ring frame comprises an electrically-insulating material.

### Claim 3 (depends on 1)

The semiconductor power device of claim 1, wherein the ring frame comprises beryllium oxide (BeO), a silicon carbide (SiC), diamond, or aluminum nitride (AlN).

### Claim 4 (depends on 1)

The semiconductor power device of claim 1, wherein the semiconductor power die comprises a field effect transistor (FET).

### Claim 5 (depends on 4)

The semiconductor power device of claim 4, further comprising:
a first set of one or more electrical conductors electrically coupling the input lead to one or more gate electrodes of the FET;
a second set of one or more electrical conductors electrically coupling one or more source electrodes of the FET to the base plate; and
a third set of one or more electrical conductors electrically coupling one or more drain electrodes of the FET to the output lead.

### Claim 6 (depends on 5)

The semiconductor power device of claim 5, wherein at least one of the first, second, or third set of one or more electrical conductors comprise at least one wirebond or conductive-ribbon.

### Claim 7 (depends on 1)

The semiconductor power device of claim 1, wherein the semiconductor power die comprises:
a silicon carbide (SiC) substrate disposed on the base plate; and
a gallium nitride (GaN) layer disposed on the SiC substrate.

### Claim 8 (depends on 1)

The semiconductor power device of claim 1, further comprising a thermal substrate disposed on the base plate, wherein the thermal substrate is thermally and electrically coupled to a set of one or more electrodes on the semiconductor power die to reduce a temperature of an active region of the semiconductor power die.

### Claim 9 (depends on 8)

The semiconductor power device of claim 8, wherein the thermal substrate comprises a top metallization layer, and further comprising a first set of one of more electrical conductors electrically coupling the set of one or more electrodes to the top metallization layer of the thermal substrate.

### Claim 10 (depends on 9)

The semiconductor power device of claim 9, further comprising a second set of one or more electrical conductors electrically coupling the top metallization layer of the thermal substrate to the output lead.

### Claim 11 (depends on 10)

The semiconductor power device of claim 10, wherein the semiconductor power device comprises a field effect transistor (FET), and wherein the set of one or more electrodes comprises a set of one or more drain electrodes, respectively.

### Claim 12 (depends on 9)

The semiconductor power device of claim 9, further comprising a second set of one or more electrical conductors electrically coupling the top metallization layer of the thermal substrate to the input lead.

### Claim 13 (depends on 12)

The semiconductor power device of claim 12, wherein the semiconductor power device comprises a field effect transistor (FET), and wherein the set of one or more electrodes comprises a set of one or more gate electrodes, respectively.

### Claim 14 (depends on 8)

The semiconductor power device of claim 8, wherein the thermal substrate comprises beryllium oxide (BeO), a silicon carbide (SiC), diamond, or aluminum nitride (AlN).

### Claim 15 (depends on 1)

The semiconductor power device of claim 1, further comprising a metal bar disposed on the base plate, wherein the metal bar is thermally and electrically coupled to a set of one or more electrodes on the semiconductor power die to reduce a temperature of an active region of the semiconductor power die.

### Claim 16 (depends on 16)

The semiconductor power device of claim 16, wherein the semiconductor power die comprises a field effect transistor (FET), and wherein the set of one or more electrodes comprises a set of one or more source electrodes of the FET, respectively.

### Claim 17

A semiconductor power device, comprising:
a base plate;
at least one frame disposed over the base plate;
an input lead disposed over the at least one frame;
an output lead disposed over the at least one frame; and
a semiconductor power die disposed over the base plate, wherein the semiconductor power die is configured to receive an input signal from the input lead and generate an output signal at the output lead.

### Claim 18 (depends on 17)

The semiconductor power device of claim 17, wherein the at least one frame comprises beryllium oxide (BeO), a silicon carbide (SiC), diamond, or aluminum nitride (AlN).

### Claim 19 (depends on 17)

The semiconductor power device of claim 17, wherein the semiconductor power die comprises a field effect transistor (FET) including at least one gate electrode electrically coupled to the input lead, at least one source electrode electrically coupled to the base plate, and at least one drain electrode electrically coupled to the output lead.

### Claim 20

A gallium-nitride (GaN) on silicon carbide (SiC) high electron mobility transistor (HEMT), comprising:
a base plate;
at least one frame disposed over the base plate;
an input lead disposed over the at least one frame;
an output lead disposed over the at least one frame;
a semiconductor power die disposed over the base plate, wherein the semiconductor power die includes a set of one or more gate electrodes configured to receive an input signal by way of the input lead, a set of one or more source electrodes electrically coupled to the base plate, and a set of one or more drain electrodes configured to produce an output signal at the output lead;
a first set of one or more electrical conductors by way the set of one or more gate electrodes receive the input signal from the input lead;
a second set of one or more electrical conductors electrically connecting the set of one or more source electrodes to the base plate; and
a third set of one or more electrical conductors by way the set of one or more drain electrodes produce the output signal at the output lead.