# US 2019/0355647 A1 · Dual-damascene zero-misalignment-via process for semiconductor packaging > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355647 A1 - Document ID: US20190355647A1 - Status: Published application - Kind: A1 - Application number: 16/527,961 - Filed: 2019-07-31 - Published: 2019-11-21 - Earliest claimed: 2017-12-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Aleksandar ALEKSOV; Hiroki TANAKA; Robert A. MAY; Kristof DARMAWIKARTA; Changhua LIU; Chung Kwang TAN; Srinivas PIETAMBARAM; Sri Ranga Sai BOYAPATI - Web page: https://patentgrep.com/patent/US20190355647A1 ## CPC - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10P 76/2042: {using lasers} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10P 76/2041: {Photolithographic processes} - H10W 20/084: {for dual-damascene structures} - H10W 20/0882: {wherein the dual damascene structure is in a photoresist layer} - H10W 46/301: {for alignment} - H10W 70/685: comprising multiple insulating layers - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package. ## Claims ### Claim 1 A semiconductor package, comprising: a buildup film, wherein one or more metal pads are disposed in the buildup film; and a plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs, wherein the plurality of dual-damascene ZMVs and the trace are disposed in the buildup film and wherein the plurality of dual-damascene ZMVs connect with the one or more metal pads in the buildup film. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and the trace has a second size in the dimension and wherein the first size is substantially equal to the second size. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein each of the one or more metal pads has a third size and wherein the third size is substantially equal to or greater than the first size. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein a sidewall of one of the plurality of dual-damascene ZMVs and a sidewall of the trace are co-planar with each other. ### Claim 5 A semiconductor package, comprising: a buildup film, wherein one or more metal pads are formed in the buildup film; a first photoimageable dielectric (PID) layer on the buildup film; a second PID layer on the first PID layer; and a plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs, wherein the plurality of dual-damascene ZMVs and the trace are disposed in the first and second PID layers, respectively, and wherein the plurality of dual-damascene ZMVs connect with the one or more metal pads in the buildup film. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein each of the first and second PID layers comprises a positive tone PID. ### Claim 7 (depends on 5) The semiconductor package of claim 5, wherein each of the first and second PID layers comprises a negative tone PID. ### Claim 8 (depends on 5) The semiconductor package of claim 5, wherein the first PID layer differs from the second PID layer. ### Claim 9 (depends on 5) The semiconductor package of claim 5, wherein the first PID layer is sensitive to a first dose of light and the second PID layer is sensitive to a second dose of light and wherein the first and second doses of light differ from each other. ### Claim 10 (depends on 5) The semiconductor package of claim 5, wherein the first PID layer is sensitive to light having a first wavelength and the second PID layer is sensitive to light having a second wavelength and wherein the first and second wavelengths differ from each other. ### Claim 11 (depends on 5) The semiconductor package of claim 5, wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and the trace has a second size in the dimension and wherein the first size is substantially equal to the second size. ### Claim 12 (depends on 5) The semiconductor package of claim 5, wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and each of the one or more metal pads has a second size in the dimension and wherein the second size is approximately equal to or greater than the first size. ### Claim 13 (depends on 5) The semiconductor package of claim 5, wherein a sidewall of one of the plurality of dual-damascene ZMVs and a sidewall of the trace are co-planar with each other. ### Claim 14 A semiconductor package, comprising: a buildup film, wherein one or more metal pads are disposed in the buildup film; a photoimageable dielectric (PID) layer on the buildup film; and a plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs, wherein the plurality of dual-damascene ZMVs and the trace are disposed in and on the PID layer, respectively, and wherein the plurality of dual-damascene ZMVs connect with the one or more metal pads in the buildup film. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the PID layer comprises a positive tone PID. ### Claim 16 (depends on 14) The semiconductor package of claim 14, wherein the PID layer comprises a negative tone PID. ### Claim 17 (depends on 14) The semiconductor package of claim 14, wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and the trace has a second size in the dimension and wherein the first size is substantially equal to the second size. ### Claim 18 (depends on 14) The semiconductor package of claim 14, wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and each of the one or more metal pads has a second size in the dimension and wherein the second size is approximately equal to or greater than the first size. ### Claim 19 (depends on 14) The semiconductor package of claim 14, wherein a sidewall of one of the plurality of dual-damascene ZMVs and a sidewall of the trace are co-planar with each other. ### Claim 20 (depends on 14) The semiconductor package of claim 14, wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and the trace has a second size in the dimension and wherein the first size is substantially equal to the second size.