# US 2019/0355646 A1 · Semiconductor structure and fabrication method thereof

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- Number: US 2019/0355646 A1
- Document ID: US20190355646A1
- Status: Published application
- Kind: A1
- Application number: 16/290,464
- Filed: 2019-03-01
- Published: 2019-11-21
- Earliest claimed: 2018-05-21
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei ZHOU
- Web page: https://patentgrep.com/patent/US20190355646A1

## CPC

- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 40/253: {Semiconductors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/8325: {Silicon carbide}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor structure includes providing a substrate and forming a plurality of fins on a surface of the substrate. Along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions. The first regions are located at both sides of the second regions. The method also includes forming first openings in the fins by removing the first regions of the fins at both sides of the gate structures until the substrate is exposed. Further, the method includes forming thermal conductive layers in the first openings, and forming doped layers on top surfaces of the thermal conductive layers. A material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of fins on a surface of the substrate, wherein, along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions; and the first regions are located at both sides of the second regions;
forming first openings in the fins by removing the first regions of the fins at both sides of the gate structures until the substrate is exposed;
forming thermal conductive layers in the first openings; and
forming doped layers on top surfaces of the thermal conductive layers,
wherein a material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.

### Claim 2 (depends on 1)

The method according to claim 1, wherein a size of the first openings along the extending direction of the fins is in a range of approximately 8 nm to 20 nm.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a depth of the first openings is in a range of approximately 800 angstroms to 3,000 angstroms.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the semiconductor structure is a PMOS transistor, and the material of the fins includes silicon germanium.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the semiconductor structure is an NMOS transistor, and the material of the fins includes a compound of a group element.

### Claim 6 (depends on 1)

The method according to claim 1, wherein:
a material of the thermal conductive layer includes silicon; and
a thickness of the thermal conductive layers is in a range of approximately 500 angstroms to 2,000 angstroms.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
a material of the thermal conductive layer includes silicon carbide; and
a thickness of the thermal conductive material films is in a range of approximately 500 angstroms to 2,000 angstroms.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
forming an isolation structure on the surface of the substrate, wherein:
a top surface of the isolation structure is lower than top surfaces of the fins; and
the isolation structure covers a portion of the sidewalls of the fins.

### Claim 9 (depends on 1)

The method according to claim 1, further comprising:
forming sidewalls on sides of the gate structures and the fins, wherein the top surfaces of the thermal conductive layers are lower than top surfaces of the sidewalls.

### Claim 10 (depends on 9)

The method according to claim 9, wherein a material of the sidewalls includes silicon nitride.

### Claim 11

A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an isolation structure and a plurality of fins on a surface of the substrate, wherein, along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions; the first regions are located at both sides of the second regions; a top surface of the isolation structure is lower than top surfaces of the fins; and the isolation structure covers a portion of sidewalls of the fins;
forming first openings in the fins by removing the first regions of the fins at both sides of the gate structures until the substrate is exposed;
forming second openings in the isolation structure by removing the portion of the isolation structure at the sidewalls of the first openings, wherein the second openings are connected with their corresponding first openings;
forming thermal conductive layers in the second openings; and
forming doped layers on top surfaces of the thermal conductive layers,
wherein a material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the sum of the sizes of one second opening and one first opening in a direction perpendicular to the extending direction of the fins is in a range of approximately 12 nm to 30 nm.

### Claim 13 (depends on 11)

The method according to claim 11, further comprising:
forming sidewalls on sides of the gate structures and the fins, wherein top surfaces of the thermal conductive layers are lower than tops of the sidewalls.

### Claim 14

A semiconductor structure, comprising:
a substrate;
a plurality of fins formed on a surface of the substrate, wherein, along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions; and the first regions are located at both sides of the second regions;
first openings formed at the first regions located at both sides of the gate structures, wherein the bottoms of the first openings expose the surface of the substrate;
thermal conductive layers formed in the first openings; and
doped layers formed on top surfaces of the thermal conductive layers,
wherein a material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.

### Claim 15 (depends on 14)

The semiconductor structure according to claim 14, wherein the size of the first openings in the extending direction of the fin is in a range of approximately 8 nm to 20 nm.

### Claim 16 (depends on 14)

The semiconductor structure according to claim 14, wherein a depth of the first openings is in a range of approximately 800 angstroms to 3,000 angstroms.

### Claim 17 (depends on 14)

The semiconductor structure according to claim 14, wherein the semiconductor structure is a PMOS transistor, and the material of the fins includes silicon germanium.

### Claim 18 (depends on 14)

The semiconductor structure according to claim 14, wherein the semiconductor structure is an NMOS transistor, and the material of the fins includes a compound of a group III-V element.

### Claim 19 (depends on 14)

The semiconductor structure according to claim 14, wherein:
a material of the thermal conductive layers includes silicon; and
a thickness of thermal conductive layers is in a range of approximately 500 angstroms to 2,000 angstroms.

### Claim 20 (depends on 11)

The semiconductor structure according to claim 11, wherein:
a material of the thermal conductive layers includes silicon carbide; and
a thickness of thermal conductive layers is in a range of approximately 500 angstroms to 2,000 angstroms.