# US 2019/0355643 A1 · Wire Bonded Package with Single Piece Exposed Heat Slug and Leads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355643 A1 - Document ID: US20190355643A1 - Status: Published application - Kind: A1 - Application number: 15/983,621 - Filed: 2018-05-18 - Published: 2019-11-21 - Earliest claimed: 2018-05-18 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Chii Shang Hong; Edmund Sales Cabatbat; Lee Shuang Wang - Web page: https://patentgrep.com/patent/US20190355643A1 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 70/461: {specially adapted for cooling} - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 90/811: {Multiple chips on leadframes} - H10W 70/429: {being the outer leads} - H10W 72/075: {of bond wires} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall. ## Claims ### Claim 1 A semiconductor device package, comprising: a die pad comprising a die attach surface and an outer surface opposite the die attach surface; a semiconductor die mounted on the die attach surface; an encapsulant material that encapsulates the semiconductor die and exposes the outer surface of the die pad at an upper side of the encapsulant material; a first lead that directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material that is opposite the upper side; and a second lead that is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material that is opposite the first sidewall, and bends towards the lower side of the encapsulant material; wherein a first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall wherein an area of the die pad is larger than the semiconductor die, and wherein the semiconductor die is mounted on the die pad such that semiconductor die is completely contained within an outer periphery of the die pad. ### Claim 2 (depends on 1) The semiconductor device package of claim 1, wherein the first lead further comprises a first vertical section that forms a bent intersection with the first lateral section and extends vertically towards the lower side of the package, wherein the second lead further comprises a second vertical section that forms a bent intersection with the second lateral section and extends vertically towards the lower side of the package, and wherein a vertical extension of the first vertical section is greater than a vertical extension of the second vertical section. ### Claim 3 (depends on 2) The semiconductor device package of claim 2, wherein the first lateral section intersects the first sidewall at an upper corner of the packaged device such that an upper surface of the first lead in the first lateral section is coplanar with the upper side of the encapsulant material, and wherein the second lateral section intersects the second sidewall such that an upper surface of the second lead in the second lateral section is vertically offset from the upper side of the encapsulant material. ### Claim 4 (depends on 1) The semiconductor device package of claim 1, wherein the die pad comprises first and second vertical edge sides that are opposite from one another and extend between the die attach surface and the outer surface, and wherein the first vertical edge side is exposed from the first sidewall of the encapsulant material. ### Claim 5 (depends on 4) The semiconductor device package of claim 4, wherein the second vertical edge side is insulated from the second sidewall by a portion of the encapsulant material, and wherein the die attach surface extends completely from the second vertical edge side to the first sidewall of the encapsulant material along a single plane. ### Claim 6 (depends on 5) The semiconductor device package of claim 5, wherein the first lateral section of the first lead and the die pad are integrally formed together. ### Claim 7 (depends on 5) The semiconductor device package of claim 5, wherein a thickness of the die pad is substantially uniform along a lateral section that extends from the second vertical edge side to the first sidewall. ### Claim 8 (depends on 5) The semiconductor device package of claim 5, wherein the die pad comprises a central section and a first outer section laterally extending from the central section to the first sidewall of the encapsulant material, wherein a thickness of the die pad is greater in the central section than in the first outer section. ### Claim 9 (canceled) ### Claim 10 A semiconductor device package, comprising: a semiconductor die; an encapsulant material that encapsulates the semiconductor die; an integrally formed electrically conductive structure that provides a die pad and a first lead for the semiconductor device package; a second lead that is partially encapsulated by the encapsulant material and is detached from the die pad, wherein the semiconductor die comprises a first terminal that faces and is electrically connected to the die pad and a second terminal facing away from the first terminal that is electrically connected to the second lead, wherein the first and second leads intersect with first and second opposite facing sidewalls of the encapsulant material, respectively, at locations that are vertically offset from one another wherein the integrally formed electrically conductive structure comprises a die attach surface and an outer surface opposite the die attach surface, wherein the outer surface of the integrally formed electrically conductive structure that is directly opposite from the semiconductor die is exposed from the encapsulant material, wherein an area of the die pad is larger than the semiconductor die, and wherein the semiconductor die is mounted on the die pad such that semiconductor die is completely contained within an outer periphery of the die pad. ### Claim 11 (depends on 10) The semiconductor device package of claim 10, wherein a vertical displacement of the first lead is greater than a vertical displacement of the second lead, the vertical displacement of the first lead being a distance between an uppermost surface of the first lead and a lowermost surface of the first lead, the vertical displacement of the second lead being a distance between an uppermost surface of the second lead and a lowermost surface of the second lead. ### Claim 12 (depends on 10) The semiconductor device package of claim 10, wherein the integrally formed electrically conductive structure comprises a substantially uniform thickness section that provides the die pad and a first lateral section of the first lead that intersects with and extends away from the first sidewall. ### Claim 13 (depends on 12) The semiconductor device package of claim 12, wherein an outer surface of the substantially uniform thickness section is exposed from the encapsulant material and is coplanar with the upper side of the encapsulant material. ### Claim 14 (depends on 10) The semiconductor device package of claim 10, wherein the integrally formed electrically conductive structure comprises a thicker central section and a thinner first outer section, wherein an outer surface of the thicker central section is exposed from the encapsulant material and is coplanar with the upper side of the encapsulant material, and wherein the thinner first outer section extends to the first sidewall. ### Claim 15 (depends on 14) The semiconductor device package of claim 14, wherein the second lead is electrically connected to the second terminal by an electrically conductive bond wire. ### Claim 16 A method of forming a semiconductor device package, the method comprising: providing an electrically conductive die pad comprising a die attach surface and an outer surface opposite the die attach surface; mounting a semiconductor die on the die attach surface; forming an encapsulant material that encapsulates the semiconductor die and exposes the outer surface of the die pad at an upper side of the encapsulant material; providing a first lead that directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material that is opposite the upper side; and providing a second lead that is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material that is opposite the first sidewall, and bends towards the lower side of the encapsulant material, wherein the first lead comprises a first lateral section that intersects the first sidewall, wherein the second lead comprises a second lateral section that intersects the second sidewall, and wherein the first and second leads are provided such that the first and second lateral sections are vertically offset from one another. ### Claim 17 (depends on 16) The method of claim 16, wherein forming the semiconductor device package comprises: providing a single lead frame comprising a first lead frame section and a second lead frame section, the first lead frame section comprising the die pad and a first set of leads connected to and extending away from a first side of the die pad, the second lead frame section comprising a second set of leads, arranging the second lead frame section to be laterally spaced apart from the die pad such that the second set of leads extend away from a second side of the die pad that is opposite the first side; wherein the first lead is provided from the first set of leads, and wherein the second lead is provided from the second set of leads. ### Claim 18 (depends on 17) The method of claim 17, wherein the second lead frame section is vertically offset from first lead frame section during formation of the encapsulant material. ### Claim 19 (depends on 17) The method of claim 17, further comprising, after mounting the semiconductor die to the die attach surface: providing electrically an electrically conductive bond wire that electrically connects the terminal of the semiconductor die to the second lead; and forming the encapsulant material on the lead frame such that the encapsulant material encapsulates the bond wires and extends to the first side of the die pad and to the second set of leads. ### Claim 20 (depends on 19) The method of claim 19, further comprising, after forming the electrically insulating encapsulant material: bending the first lead such that the first lead comprises a first vertical section that forms a bent intersection with the first lateral section and extends towards the lower side of the package; and bending the second lead such that the second lead comprises a second vertical section that forms a bent intersection with the second lateral section and extends towards the lower side of the package, and wherein a vertical extension of the first vertical section is greater than a vertical extension of the second vertical section. ### Claim 21 (depends on 1) The semiconductor device package of claim 1, wherein the first sidewall of the encapsulant material extends from an intersection with the first sidewall and the upper side of the encapsulant material to an intersection with the first sidewall and a lower side of the encapsulant material, the lower side of the encapsulant material being opposite from the upper side, wherein the first lead comprises a second vertical edge side that extends from the upper side into the encapsulant material and a bent intersection that is outside of the encapsulant material, and wherein the first lead comprises an upper surface that is completely exposed from the encapsulant material between the second vertical edge side and the bent intersection. ### Claim 22 (depends on 21) The semiconductor device package of claim 21, wherein the upper surface of the first lead is coplanar with the upper side of the encapsulant material. ### Claim 23 (depends on 21) The semiconductor device package of claim 21, wherein the first sidewall extends along a single plane between the intersection with the upper side of the encapsulant material and the intersection with the lower side of the encapsulant material. ### Claim 24 (depends on 1) The semiconductor device package of claim 1, wherein the second lead is separated from the semiconductor die by a region of the encapsulant material, and wherein the second lead is electrically connected to the second terminal by an electrically conductive bond wire. ### Claim 25 (depends on 24) The semiconductor device package of claim 24, wherein an end of the second lead is laterally separated from an end of the semiconductor die in a lateral direction that is parallel to the upper side of the encapsulant body.