# US 2019/0355622 A1 · Method for fabricating a semiconductor device and a semiconductor device

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- Number: US 2019/0355622 A1
- Document ID: US20190355622A1
- Status: Published application
- Kind: A1
- Application number: 16/414,818
- Filed: 2019-05-17
- Published: 2019-11-21
- Earliest claimed: 2018-05-17
- Assignees: 3-5 Power Electronics GmbH
- Applicants: 3-5 Power Electronics GmbH
- Inventors: Volker DUDEK
- Web page: https://patentgrep.com/patent/US20190355622A1

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/01: Manufacture or treatment
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/3421: {Arsenides}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/22: using masks
- H10P 50/646: {of Group III-V materials}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/043: {of planar diodes}
- H10D 12/032: {of vertical IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor semi-finished product having a top surface and a bottom surface, the semiconductor semi-finished product having a plurality of mutually adjacent stacked semiconductor devices, wherein the semiconductor devices have a substrate layer with a III-V material or with germanium and the substrate layer being disposed on or near the bottom surface;
arranging on the substrate layer, a first semiconductor layer of a first conductivity type and arranging on the first semiconductor layer at least one second semiconductor layer of a second conductivity type, wherein the first and second semiconductor layers are formed of a III-V material or consist of a III-V material and the first and second conductivity types are different;
forming between two immediately adjoining semiconductor devices, a scribe line with a width on the top surface of the semiconductor semi-finished product;
dicing the semiconductor devices along the scribe line;
applying to the top surface (102) of the semiconductor semi-finished product, prior to dicing, a mask layer that covers the semiconductor devices and leaves at least a portion of the scribe line uncovered;
performing, after applying the mask layer, ion implantation for at least partial amorphization and/or insulation, and the ion implantation has at least one implantation step with an energy of at least 500 keV;
removing the mask layer after the ion implantation;
dicing the semiconductor devices after the mask layer is removed; and
coating, prior to applying the mask layer, the top surface of the semiconductor semi-finished product via a chemical vapor deposition with a passivation layer having a layer thickness of at least 100 nm.

### Claim 2 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer each are formed of a GaAs compound or consist of a GaAs compound.

### Claim 3 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein via the ion implantation, a deep region between the top surface up to the first semiconductor layer or a deep region between the top surface and including the second semiconductor layer or a deep region between the top surface up to the substrate layer is amorphized and/or insulated.

### Claim 4 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein hydrogen ions and/or helium ions are implanted.

### Claim 5 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein during implantation, an acceleration energy of the ions is changed between a minimum value and a maximum value, and wherein the minimum value is at least 50 keV and the maximum value is at most 300 MeV.

### Claim 6 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein an implantation dosage during implantation is between 1010 cm−2 and 1016 cm−2.

### Claim 7 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein, prior to dicing, the mask layer is removed via a wet etching process.

### Claim 8 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein metallic contact surfaces are formed on the top surface and/or on the bottom surface prior to the formation of the mask layer.

### Claim 9 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein after the application of the mask layer, a mesa etching process is carried out.

### Claim 10 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein the scribe line is amorphized and/or insulated over a width of at least 30 μm and at most 300 μm.

### Claim 11 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein a metal is used for the mask layer.

### Claim 12 (depends on 1)

The method of fabricating a semiconductor device according to claim 1, wherein, for the mask layer titanium or aluminum is used.

### Claim 13

A stacked semiconductor device comprising:
a top surface;
a bottom surface; and
at least one side surface that connects the top surface with the bottom surface,
wherein the bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer,
wherein, on the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged, wherein the first and second semiconductor layers are formed of a III-V material or consist of a III-V material,
wherein the first and second conductivity types are different,
wherein the top surface is at least partially formed by a passivation layer,
wherein along the side surface, an amorphized and/or insulating region extending to a depth is formed, and
wherein the depth is perpendicular or substantially perpendicular to the layer stack.

### Claim 14 (depends on 13)

The stacked semiconductor device according to claim 13, wherein the first semiconductor layer and the second semiconductor layer each are formed of a GaAs compound or consist of a GaAs compound.

### Claim 15 (depends on 13)

The stacked semiconductor device according to claim 13, wherein the depth is at least 0.5 μm or at least 5 μm or at least 30 μm or a deep region is formed between the top surface up to the first semiconductor layer or a deep region is formed between the top surface and including the second semiconductor layer or a deep region is formed between the top surface up to the substrate layer.

### Claim 16 (depends on 13)

The stacked semiconductor device according to claim 13, wherein a contact surface on a top surface and/or rear side contact layer has gold, silver and/or palladium.

### Claim 17 (depends on 13)

The stacked semiconductor device according to claim 13, wherein the semiconductor device has an overall height of at least 10 μm and at most 1000 μm.