# US 2019/0355583 A1 · Method of forming drain extended mos transistors for high voltage circuits

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- Number: US 2019/0355583 A1
- Document ID: US20190355583A1
- Status: Published application
- Kind: A1
- Application number: 16/275,521
- Filed: 2019-02-14
- Published: 2019-11-21
- Earliest claimed: 2013-07-22
- Assignees: Longitude Flash Memory Solutions Ltd.
- Applicants: Longitude Flash Memory Solutions Ltd.
- Inventors: Sungkwon Lee; Igor G. Kouznetsov; Gyu-Chul Kim
- Web page: https://patentgrep.com/patent/US20190355583A1

## CPC

- H10P 30/22: using masks
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/836: {comprising EDMOS}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0167: {Manufacturing their channels}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

## Claims

### Claim 1

A method comprising:
implanting ions of a first-type at a first energy level in a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate to form a first DE_MOS transistor; and
implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate to adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor.

### Claim 2 (depends on 1)

The method of claim 1 wherein implanting ions of the first-type at the first energy level in the drain portion of the first DE_MOS transistor, comprises concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate to adjust a voltage threshold of a first high-voltage metal-on-semiconductor (HV_MOS) transistor in the HV_MOS region.

### Claim 3 (depends on 2)

The method of claim 2 further comprising implanting ions of a second-type at the first energy level in a drain portion of a second DE_MOS transistor in the DE_MOS region while concurrently implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of a second HV_MOS transistor in the HV_MOS region.

### Claim 4 (depends on 3)

The method of claim 3 further comprising implanting ions of the second-type at the second energy level in the LV_MOS region of the substrate to adjust a voltage threshold of a second LV_MOS transistor, while concurrently implanting ions of the second-type at the second energy level in the drain portion of the second DE_MOS transistor to form a drain extension of the second DE_MOS transistor.

### Claim 5 (depends on 4)

The method of claim 4 wherein:
implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of the second HV_MOS transistor, further comprises concurrently implanting ions of the second-type at the first energy level in the DE_MOS region to form a source portion of the first DE_MOS transistor; and
implanting ions of the first-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of the first HV_MOS transistor, further comprises concurrently implanting ions of the first-type at the first energy level in the DE_MOS region to form a source portion of the second DE_MOS transistor.

### Claim 6 (depends on 5)

The method of claim 5 wherein the second energy level is lower than the first energy level.

### Claim 7 (depends on 5)

The method of claim 5 further comprising forming sources and drains in the first DE_MOS transistor and the second DE_MOS transistor, the first LV_MOS transistor and the second LV_MOS transistor, and the first HV_MOS transistor and the second HV_MOS transistor.

### Claim 8 (depends on 1)

The method of claim 1 wherein the DE_MOS formed is in an input/output (I/O) cell of a non-volatile memory (NVM).

### Claim 9 (depends on 1)

The method of claim 1 wherein the DE_MOS formed is on pitch with a non-volatile memory (NVM) array of a NVM.

### Claim 10 (depends on 1)

The method of claim 1 further comprising forming a mask over the substrate exposing a part of the drain portion of the first DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the first DE_MOS transistor.

### Claim 11

A method comprising:
forming a first threshold voltage adjust mask over a surface of a substrate to expose a high-voltage metal-on-semiconductor (HV_MOS) transistor in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate, and to expose a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of the substrate;
implanting ions of a first-type at a first energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in the HV_MOS transistor to adjust a voltage threshold of the HV_MOS;
forming a second threshold voltage adjust mask over the surface of a substrate to expose a low-voltage metal-on-semiconductor (LV_MOS) transistor in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate, and to expose the drain portion of the DE_MOS transistor; and
implanting ions of the first-type at a second energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the LV_MOS transistor to adjust a voltage threshold of the LV_MOS.

### Claim 12 (depends on 11)

The method of claim 11 wherein the second energy level is lower than the first energy level.

### Claim 13 (depends on 11)

The method of claim 11 further comprising forming sources and drains in the DE_MOS transistor the LV_MOS transistor, and HV_MOS transistor.

### Claim 14 (depends on 11)

The method of claim 11 wherein the DE_MOS formed is in an input/output (I/O) cell of a non-volatile memory (NVM).

### Claim 15 (depends on 11)

The method of claim 11 wherein the DE_MOS formed is on pitch with a non-volatile memory (NVM) array of a NVM.

### Claim 16 (depends on 11)

The method of claim 11 further comprising forming a mask over the substrate exposing a part of the drain portion of the DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the DE_MOS transistor.

### Claim 17

A method comprising:
implanting ions of a first-type at a first energy level in a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate to form a DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate to adjust a voltage threshold of a HV_MOS transistor in the HV_MOS region.

### Claim 18 (depends on 17)

The method of claim 17 further comprising implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate to adjust a voltage threshold of a LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the DE_MOS transistor to form a drain extension of the DE_MOS transistor.

### Claim 19 (depends on 18)

The method of claim 18 wherein the second energy level is lower than the first energy level.

### Claim 20 (depends on 18)

The method of claim 18 further comprising forming a first gate oxide for the DE_MOS transistor while concurrently forming a second gate oxide for the HV_MOS transistor.