# US 2019/0319782 A1 · Combined sha2 and sha3 based xmss hardware accelerator

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- Number: US 2019/0319782 A1
- Document ID: US20190319782A1
- Status: Published application
- Kind: A1
- Application number: 16/455,950
- Filed: 2019-06-28
- Published: 2019-10-17
- Earliest claimed: 2019-06-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: SANTOSH GHOSH; Vikram Suresh; Sanu Mathew; Manoj Sastry; Andrew H. Reinders; Raghavan Kumar; Rafael Misoczki
- Web page: https://patentgrep.com/patent/US20190319782A1

## CPC

- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- G06F 7/503: using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
- G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/3239: {involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD}
- H04L 9/3247: {involving digital signatures}
- H04L 9/50: {using hash chains, e.g. blockchains or hash trees}
- H04L 2209/122: Hardware reduction or efficient architectures
- H04L 2209/125: Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY

## Abstract

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

## Claims

### Claim 1

An apparatus, comprising:
a computer readable memory;
an XMSS operations logic to manage XMSS functions;
a chain function controller to manage chain function algorithms;
a secure hash algorithm-2 (SHA2) accelerator;
a secure hash algorithm-3 (SHA3) accelerator; and
a register bank shared between the SHA2 accelerator and the SHA3 accelerator.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising logic to:
receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and
determine a selected accelerator from at least one of the SHA2 accelerator or the SHA3 accelerator;
apply the set of inputs to the selected accelerator.

### Claim 3 (depends on 2)

The apparatus of claim 2, further comprising logic to:
assert a busy signal on a communication bus; and
switch to a protected mode in which external read/write operations are disregarded.

### Claim 4 (depends on 3)

The apparatus of claim 3, further comprising logic to:
determine whether the XMSS operation utilizes a one-time signature function, and in response to a determination that the XMSS operation requires a one-time signature function, to:
apply a one-time signature function process to the set of XMSS inputs; and
invoke the chain function controller to apply a chain function to facilitate the one-time signature function.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the SHA2 accelerator comprises a 64 bit datapath that is configurable to perform a single SHA2-512 round of operations or to perform two SHA2-256 rounds of operation in parallel.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively apply a carry operation when the SHA2 accelerator is configured to perform two SHA2-256 rounds of operation in parallel.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively terminate a carry operation when the SHA2 accelerator is configured to a single SHA2-512 round of operation.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the SHA3 accelerator is configurable to perform a SHAKE-128 function or to perform a SHAKE-256 operation.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the SHA3 accelerator comprises:
a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and
logic to:
receive a 256 bit message input;
perform a set of 24 SHA3 rounds; and
generate a 128 bit output.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the SHA3 accelerator comprises:
a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and
logic to:
receive a 512 bit message input;
perform two sets of 24 SHA3 rounds; and
generate a 256 bit output.

### Claim 11

An electronic device, comprising:
a processor; and
a hardware accelerator for an authentication logic, the hardware accelerator comprising:
a computer readable memory;
an XMSS operations logic to manage XMSS functions;
a chain function controller to manage chain function algorithms;
a secure hash algorithm-2 (SHA2) accelerator;
a secure hash algorithm-3 (SHA3) accelerator; and
a register bank shared between the SHA2 accelerator and the SHA3 accelerator.

### Claim 12 (depends on 11)

The electronic device of claim 11, the hardware accelerator further comprising logic to:
receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation;
determine a selected accelerator from at least one of the SHA2 accelerator or the SHA3 accelerator; and
apply the set of inputs to the selected accelerator.

### Claim 13 (depends on 12)

The electronic device of claim 12, the hardware accelerator further comprising logic to:
assert a busy signal on a communication bus; and
switch to a protected mode in which external read/write operations are disregarded.

### Claim 14 (depends on 13)

The electronic device of claim 13, the hardware accelerator further comprising logic to:
determine whether the XMSS operation utilizes a one-time signature function, and in response to a determination that the XMSS operation requires a one-time signature function, to:
apply a one-time signature function process to the set of XMSS inputs; and
invoke the chain function controller to apply a chain function to facilitate the one-time signature function.

### Claim 15 (depends on 11)

The electronic device of claim 11, wherein the SHA2 accelerator comprises a 64 bit datapath that is configurable to perform a single SHA2-512 round of operations or to perform two SHA2-256 rounds of operation in parallel.

### Claim 16 (depends on 15)

The electronic device of claim 15, wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively apply a carry operation when the SHA2 accelerator is configured to perform two SHA2-256 rounds of operation in parallel.

### Claim 17 (depends on 15)

The electronic device of claim 15, wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively terminate a carry operation when the SHA2 accelerator is configured to a single SHA2-512 round of operation.

### Claim 18 (depends on 11)

The electronic device of claim 11, wherein the SHA3 accelerator is configurable to perform a SHAKE-128 function or to perform a SHAKE-256 operation.

### Claim 19 (depends on 18)

The electronic device of claim 18, wherein the SHA3 accelerator comprises:
a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and
logic to:
receive a 256 bit message input;
perform a set of 24 SHA3 rounds; and
generate a 128 bit output.

### Claim 20 (depends on 18)

The electronic device of claim 18, wherein the SHA3 accelerator comprises:
a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and
logic to:
receive a 512 bit message input;
perform two sets of 24 SHA3 rounds; and
generate a 256 bit output.