# US 2019/0319136 A1 · Inverted t channel field effect transistor (itfet) including a superlattice

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- Number: US 2019/0319136 A1
- Document ID: US20190319136A1
- Status: Published application
- Kind: A1
- Application number: 16/380,149
- Filed: 2019-04-10
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: Atomera Incorporated
- Applicants: Atomera Incorporated
- Inventors: Robert John Stephenson
- Web page: https://patentgrep.com/patent/US20190319136A1

## CPC

- H10D 30/6748: {having a multilayer structure or superlattice structure}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/8161: {potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices (lateral superlattices, lateral surface superlattices H10D62/8181)}
- H10D 62/8162: {having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation}
- H10P 14/3451: {Structure}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
an inverted T channel on the substrate and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
source and drain regions on opposing ends of the inverted T channel; and
a gate overlying the inverted T channel between the source and drain regions.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1 wherein the gate comprises a gate insulator overlying the superlattice channel layer, and a gate electrode overlying the gate insulator.

### Claim 4 (depends on 1)

The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon.

### Claim 5 (depends on 1)

The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

### Claim 7 (depends on 1)

The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

### Claim 8 (depends on 1)

The semiconductor device of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.

### Claim 9 (depends on 1)

The semiconductor device of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

### Claim 10

A semiconductor device comprising:
a semiconductor-on-insulator (SOI) substrate;
an inverted T channel on the SOI substrate and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
source and drain regions on opposing ends of the inverted T channel; and
a gate overlying the inverted T channel between the source and drain regions and comprising a gate insulator overlying the superlattice channel layer, and a gate electrode overlying the gate insulator.

### Claim 11 (depends on 10)

The semiconductor device of claim 10 wherein the base semiconductor monolayers comprise silicon.

### Claim 12 (depends on 10)

The semiconductor device of claim 10 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

### Claim 13 (depends on 10)

The semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises oxygen.

### Claim 14 (depends on 10)

The semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

### Claim 15 (depends on 10)

The semiconductor device of claim 10 wherein all of the base semiconductor portions are a same number of monolayers thick.

### Claim 16 (depends on 10)

The semiconductor device of claim 10 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

### Claim 17

A semiconductor device comprising:
a substrate;
an inverted T channel on the substrate and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
source and drain regions on opposing ends of the inverted T channel; and
a gate overlying the inverted T channel between the source and drain regions.

### Claim 18 (depends on 17)

The semiconductor device of claim 17 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.

### Claim 19 (depends on 17)

The semiconductor device of claim 17 wherein the gate comprises a gate insulator overlying the superlattice channel layer, and a gate electrode overlying the gate insulator.

### Claim 20 (depends on 17)

The semiconductor device of claim 17 wherein all of the base semiconductor portions are a same number of monolayers thick.

### Claim 21 (depends on 17)

The semiconductor device of claim 17 wherein at least some of the base semiconductor portions are a different number of monolayers thick.