# US 2019/0319086 A1 · Integrated High Voltage Capacitor

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- Number: US 2019/0319086 A1
- Document ID: US20190319086A1
- Status: Published application
- Kind: A1
- Application number: 16/377,070
- Filed: 2019-04-05
- Published: 2019-10-17
- Earliest claimed: 2018-04-16
- Assignees: Semtech Corporation
- Applicants: Semtech Corporation
- Inventors: Christopher David Ainsworth
- Web page: https://patentgrep.com/patent/US20190319086A1

## CPC

- H10D 1/692: {Electrodes}
- H10W 20/496: {Capacitor integral with wiring layers}
- H03F 3/08: controlled by light
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/47: Resistors having no potential barriers
- H10D 1/714: {having horizontal extensions}
- H10F 30/225: the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H10F 77/933: {for devices having potential barriers}
- H10F 77/953: {for devices having potential barriers}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 44/401: {Resistive arrangements (H10W44/20, H10W42/80 take precedence)}
- H10W 72/075: {of bond wires}
- H10W 90/00: Package configurations
- H03F 2200/165: A filter circuit coupled to the input of an amplifier
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/50: Bond wires
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 76/132: having other interconnections through an insulated passage in the conductive base
- H10W 90/732: {between stacked chips}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03F: AMPLIFIERS
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die;
a build-up interconnect structure including an integrated capacitor formed over the semiconductor die, wherein the integrated capacitor includes a plurality of interdigitated fingers; and
a high voltage input coupled to the integrated capacitor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further including a transimpedance amplifier formed in the semiconductor die.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further including an avalanche photodiode disposed adjacent to the semiconductor die and electrically connected to the integrated capacitor.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further including a conductive epoxy disposed between the avalanche photodiode and semiconductor die.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of interdigitated fingers are interdigitated vertically and horizontally.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further including a guard ring formed around the integrated capacitor.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further including an integrated resistor formed over the semiconductor die, wherein the integrated capacitor is coupled to the high voltage input through the integrated resistor.

### Claim 8

A semiconductor device, comprising:
a semiconductor die; and
an integrated capacitor formed over the semiconductor die, wherein the integrated capacitor is configured to receive a high voltage signal.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the integrated capacitor includes a first conductive layer comprising a first plurality of interdigitated fingers.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the integrated capacitor includes a second conductive layer comprising a second plurality of interdigitated fingers formed over the first conductive layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further including a conductive via formed between a first finger of the first plurality of interdigitated fingers and a second finger of the second plurality of interdigitated fingers.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further including an integrated resistor formed over the semiconductor die, wherein the capacitor is configured to receive the high voltage signal through the integrated resistor.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further including:
a transimpedance amplifier formed in the semiconductor die; and
a photodiode disposed adjacent to the semiconductor die.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further including a conductive epoxy or solder disposed between the semiconductor die and photodiode.

### Claim 15

A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming an integrated capacitor over the semiconductor die; and
coupling the integrated capacitor to a high voltage input of the semiconductor device.

### Claim 16 (depends on 15)

The method of claim 15, further including forming the integrated capacitor by:
forming a first conductive layer over the semiconductor die; and
patterning the first conductive layer to include,
a first bus bar,
a second bus bar oriented parallel to the first bus bar,
a first plurality of fingers extending from the first bus bar toward the second bus bar, and
a second plurality of fingers extending from the second bus bar toward the first bus bar.

### Claim 17 (depends on 16)

The method of claim 16, further including patterning the first conductive layer to include a guard ring around the first bus bar, second bus bar, first plurality of fingers, and second plurality of fingers.

### Claim 18 (depends on 16)

The method of claim 16, further including:
forming a second conductive layer over the first conductive layer; and
patterning the second conductive layer to include a third plurality of fingers.

### Claim 19 (depends on 15)

The method of claim 15, further including:
providing a contact pad coupled to the integrated capacitor;
forming an insulating layer over the contact pad;
forming an opening in the insulating layer over the contact pad; and
disposing a photodiode over the opening with a conductive material between the contact pad and photodiode.

### Claim 20 (depends on 19)

The method of claim 19, further including forming a bond wire from the photodiode to the semiconductor die.