# US 2019/0319082 A1 · Chip on film package and display device including the chip on film package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0319082 A1 - Document ID: US20190319082A1 - Status: Published application - Kind: A1 - Application number: 16/385,297 - Filed: 2019-04-16 - Published: 2019-10-17 - Earliest claimed: 2018-04-17 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Ki-Soo NAM; Gi Young KANG - Web page: https://patentgrep.com/patent/US20190319082A1 ## CPC - G02F 1/13458: {Terminal pads} - H10K 59/129: Chiplets - G02F 1/13452: {Conductors connecting driver circuitry and terminals of panels} - H10D 86/411: {characterised by materials, geometry or structure of the substrates} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/688: {Flexible insulating substrates} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 72/07254: {changes in dispositions} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip on film package includes: a base substrate having an output pad region; a plurality of output pads disposed in the output pad region of the base substrate, wherein the output pads are arranged in a zigzag configuration on the base substrate; a plurality of output pad wirings connected to the output pads, respectively; and a protection layer disposed on the output pad wirings. The protection layer is disposed on the output pad wirings disposed between two adjacent output pads, arranged in a first direction. ## Claims ### Claim 1 A chip on film package, comprising: a base substrate having an output pad region; a plurality of output pads disposed in the output pad region of the base substrate, wherein the output pads are arranged in a zigzag configuration on the base substrate; a plurality of output pad wirings connected to the output pads, respectively; and a protection layer disposed on the output pad wirings, wherein the protection layer is disposed on the output pad wiring disposed between two adjacent output pads, arranged in a first direction, among the output pads. ### Claim 2 (depends on 1) The chip on film package of claim 1, wherein the output pad region is located adjacent to a first side of the base substrate, and wherein the output pad region includes: a first region located adjacent to the first side; and a second region located adjacent to the first region and spaced apart from the first side in a second direction that is perpendicular to the first direction. ### Claim 3 (depends on 2) The chip on film package of claim 2, wherein the output pads include: lower output pads arranged along the first direction in the first region of the output pad region; and upper output pads arranged along the first direction in the second region of the output pad region, wherein the lower and upper output pads are alternately disposed in the first direction. ### Claim 4 (depends on 3) The chip on film package of claim 3, wherein the lower output pads do not overlap the upper output pads in the second direction. ### Claim 5 (depends on 3) The chip on film package of claim 3, wherein the base substrate further includes: an input pad region located adjacent to a second side, opposite to the first side, of the base substrate, and wherein the chip on film package further comprises: a plurality of input pads disposed in the input pad region of the base substrate; and a driving integrated circuit chip disposed on the base substrate and between the output pads and the input pads. ### Claim 6 (depends on 5) The chip on film package of claim 5, wherein the output pad wirings include: lower output pad wirings connected to the lower output pads, respectively; and upper output pad wirings connected to the upper output pads, respectively, wherein a first side of each of the lower and upper output pad wirings is connected to a respective output pad of the plurality of output pads, and a second side of each of the lower and upper output pad wirings is connected to the driving integrated circuit chip. ### Claim 7 (depends on 6) The chip on film package of claim 6, wherein the lower output pad wiring disposed between two adjacent upper output pads along the first direction among the upper output pads is completely covered by the protection layer. ### Claim 8 (depends on 6) The chip on film package of claim 6, wherein the protection layer has a protrusion that covers the lower output pad wiring disposed between the two adjacent upper output pads arranged in the first direction. ### Claim 9 (depends on 8) The chip on film package of claim 8, wherein the protrusion of the protection layer is disposed on the lower output pad wiring disposed between the two adjacent upper output pads arranged in the first direction, and exposes a portion of the lower output pad wiring located adjacent to a first lower output pad of the lower output pads such that the protrusion is spaced apart from the first lower output pad by a predetermined distance. ### Claim 10 (depends on 9) The chip on film package of claim 9, wherein a first distance is a distance between the protrusion of the protection layer and the first lower output pad in the second direction, and a second distance is a distance between the first lower output pad and an upper output pad of the two adjacent upper output pads in the second direction, wherein the first distance is less than the second distance. ### Claim 11 (depends on 6) The chip on film package of claim 6, wherein the protection layer has an opening exposing the output and input pads and the driving integrated circuit chip, and is disposed on the entire base substrate to cover the output pad wirings. ### Claim 12 (depends on 11) The chip on film package of claim 11 wherein a height from an upper surface of the base substrate to an upper surface the protection layer is greater than a height from the upper surface of the base substrate to an upper surface of each of the output and input pads. ### Claim 13 (depends on 1) The chip on film package of claim 1, wherein the plurality of the output pads include: first through (M)th lower output pads, wherein M is an integer greater than 1, and first through (N)th upper output pads, wherein N is an integer greater than 1, and wherein the plurality of the output pad wirings include: first through (P)th lower output pad wirings, wherein P is an integer greater than 1; and first through (Q)th upper output pad wirings, wherein Q is an integer greater than 1. ### Claim 14 (depends on 13) The chip on film package of claim 13, wherein the first through (M)th lower output pads and the first through (N)th upper output pads are alternately arranged along the first direction in different rows, and a (K)th lower output pad among the first through (M)th lower output pads is connected to an (L)th lower output pad wiring among the first through (P)th lower output pad wirings, wherein K is an integer between 1 and M and L is an integer between 1 and M, and wherein a (G)th upper output pad among the first through (N)th upper output pads is connected to an (H)th upper output pad wiring among the first through (Q)th upper output pad wirings, wherein G is an integer between 1 and M, and H is an integer between 1 and M. ### Claim 15 (depends on 14) The chip on film package of claim 14, wherein the (L)th lower output pad wiring disposed between the (G)th upper output pad and a (G+1)th upper output pad is completely covered by the protection layer. ### Claim 16 A display device, comprising: a display panel having a pixel region and a pad region, the display panel including: a plurality of pixel structures disposed in the pixel region; and a plurality of pad electrodes disposed in the pad region, wherein the pad electrodes are arranged in a zigzag configuration; a chip on film package including: a base substrate having an output pad region; a plurality of output pads disposed in the output pad region of the base substrate, wherein the output pads are arranged in a zigzag configuration on the base substrate; a plurality of output pad wirings connected to the output pads, respectively; and a protection layer disposed on the output pad wirings, wherein the output pads overlap the pad electrodes of the display panel, and the protection layer is disposed on the output pad wiring disposed between two adjacent output pads, arranged in a first direction, among the output pads; and an external device connected to the chip on film package, wherein the external device generates a plurality of signals that are provided to the display panel. ### Claim 17 (depends on 16) The display device of claim 16, wherein the plurality of the output pads include: first through (M)th lower output pads, wherein M is an integer greater than 1, and first through Nth upper output pads, wherein N is an integer greater than 1, and wherein the plurality of the output pad wirings include: first through (P)th lower output pad wirings, wherein P is an integer greater than 1; and first through (Q)th upper output pad wirings, wherein Q is an integer greater than 1. ### Claim 18 (depends on 17) The display device of claim 17, wherein the first through (M)th lower output pads and the first through (N)th upper output pads are alternately arranged along the first direction in different rows, and a (K)th lower output pad among the first through (M)th lower output pads is connected to an (L)th lower output pad wiring among the first through (P)th lower output pad wirings, wherein K is an integer between 1 and M and L is an integer between 1 and M, and wherein a (G)th upper output pad among the first through (N)th upper output pads is connected to an (H)th upper output pad wiring among the first through (Q)th upper output pad wirings, wherein G is an integer between 1 and M, and wherein H is an integer between 1 and M. ### Claim 19 (depends on 18) The display device of claim 18, wherein the (L)th lower output pad wiring disposed between the (G)th upper output pad and a (G+1)th upper output pad is completely covered by the protection layer. ### Claim 20 (depends on 18) The display device of claim 18, wherein the plurality of the pad electrodes include: first through (R)th lower pad electrodes, wherein R is an integer greater than 1; and first through (S)th upper pad electrodes, wherein S is an integer greater than 1, wherein the first through (R)th lower pad electrodes and the first through (S)th upper pad electrodes are alternately arranged along the first direction in different rows, and wherein an (E)th lower pad electrode among the first through (R)th lower pad electrodes is connected to the (G)th upper output pad, wherein E is an integer between 1 and R, and an (F)th upper pad electrode among the first through (S)th upper pad electrodes is connected to the (K)th lower output pad, wherein F is an integer between 1 and S.