# US 2019/0319040 A1 · Three-dimensional memory device containing bidirectional taper staircases and methods of making the same

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- Number: US 2019/0319040 A1
- Document ID: US20190319040A1
- Status: Published application
- Kind: A1
- Application number: 15/950,356
- Filed: 2018-04-11
- Published: 2019-10-17
- Earliest claimed: 2018-04-11
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Yasushi Ishii; Jun Akaiwa; Kiyokazu Shishido; Hiroyuki Ogawa
- Web page: https://patentgrep.com/patent/US20190319040A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/30: characterised by the memory core region
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/30: characterised by the memory core region
- H10B 43/40: characterised by the peripheral circuit region
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10B 43/10: characterised by the top-view layout
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 95/062: {involving a dielectric removal step}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.

## Claims

### Claim 1

A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
a contact well set that includes four contact wells extending through a respective upper region of the alternating stack,
wherein the contact well set comprises a rectangular opening extending through the alternating stack and four peripheral sidewalls located at a periphery of the rectangular opening;
wherein the four contact wells contact a common vertical line extending along a vertical direction that is perpendicular to a top surface of the substrate;
wherein a bottommost horizontal surface of each contact well of the four contact wells contacts the common vertical line; and
wherein each of the four contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.

### Claim 2 (depends on 1)

The three-dimensional memory device of claim 1, wherein each set of stepped surfaces within a respective one of the four contact wells comprises stepped surfaces of the insulating layers.

### Claim 3 (depends on 1)

The three-dimensional memory device of claim 1, wherein each set of stepped surfaces within a respective one of the four contact wells comprises stepped surfaces of the electrically conductive layers.

### Claim 4 (depends on 1)

The three-dimensional memory device of claim 1, wherein each set of stepped surfaces within a respective one of the four contact wells comprises a respective set of L-shaped horizontal surfaces.

### Claim 5 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
horizontal surfaces within each contact well of the four contact wells are vertically offset from any other horizontal surface located within any other contact well of the four contact wells; and
each of the four peripheral sidewalls of the contact well set vertically extends from a topmost layer within the alternating stack to top surfaces of four different layers within the alternating stack that are vertically offset from each other.

### Claim 6

(canceled)

### Claim 7 (depends on 22)

The three-dimensional memory device of claim 22, wherein the contact well set has a vertical cross-sectional profile along a vertical plane that is parallel to the first horizontal direction, and wherein the vertical cross-sectional profile that includes a stepwise descending vertical cross-sectional profile as a function of a distance from the third peripheral sidewall toward the fourth peripheral sidewall along the first horizontal direction, followed by a vertical step at one of the third vertical surface and the fourth vertical surface, and then followed by a stepwise ascending vertical cross-sectional profile as a function of the distance from the third peripheral sidewall toward the fourth peripheral sidewall along the first horizontal direction.

### Claim 8 (depends on 7)

The three-dimensional memory device of claim 7, wherein each horizontal surface within the stepwise descending vertical cross-sectional profile is vertically offset from any horizontal surface within the stepwise ascending vertical cross-sectional profile by the vertical step.

### Claim 9 (depends on 1)

The three-dimensional memory device of claim 1, wherein the four peripheral sidewalls define a single continuous cavity overlying the set of two four contact wells.

### Claim 10

(canceled)

### Claim 11 (depends on 1)

The three-dimensional memory device of claim 1, further comprising:
a retro-stepped dielectric material portion located over the contact well set; and
contact via structures extending at least from a top surface of the retro-stepped dielectric material portion and contacting a subset of the electrically conductive layers that are on, or underneath, horizontal surfaces of the four sets of stepped surfaces of the contact well set.

### Claim 12 (depends on 21)

The three-dimensional memory device of claim 21, further comprising bit lines which extend in the second horizontal direction.

### Claim 13 (depends on 12)

The three-dimensional memory device of claim 12, wherein:
the memory stack structures are located in a memory plane of a vertical NAND memory device;
the electrically conductive layers comprise word lines of the vertical NAND memory device which extend in the first horizontal direction;
the set of contact wells is located in the memory plane; and
at least some of the memory stack structures are located in the memory plane between the set of contact wells and a word line decoder region of the memory plane.

### Claim at position 14

-20. (canceled)

### Claim 21 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the four peripheral sidewalls are adjoined to each other at four vertical edges of the rectangular opening;
the four peripheral sidewalls comprise a first peripheral sidewall and a second peripheral sidewall that laterally extend along a first horizontal direction and a third peripheral sidewall and a fourth peripheral sidewall that laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction;
each of the four contact wells contains a respective well edge that coincides with a respective one of the four vertical edges of the rectangular opening; and
the first and second stepped surfaces within each of the four contact wells have a stepwise descending vertical profile along the respective first and second horizontals direction from the respective well edge to the common vertical line.

### Claim 22 (depends on 21)

The three-dimensional memory device of claim 21, wherein:
the four contact wells are located in the rectangular opening and are laterally separated from each other by four vertical surfaces having a respective vertical edge that is located within the common vertical line; and
the four vertical surfaces comprise a first vertical surface and a second vertical surface located within a first vertical plane between the first peripheral sidewall and the second peripheral sidewall, and comprises a third vertical surface and a fourth vertical surface located within a second vertical plane between the third peripheral vertical sidewall and the fourth peripheral sidewall.

### Claim 23 (depends on 22)

The three-dimensional memory device of claim 22, wherein:
the common vertical line is located at an intersection of the first vertical plane and the second vertical plane; and
each of the four contact wells has a respective rectangular periphery defined by a respective one of the first vertical surface and the second vertical surface, a respective one of the third vertical surface and the fourth vertical surface, a respective segment of one the first peripheral sidewall and the second peripheral sidewall, and a respective segment of one the third peripheral sidewall and the fourth peripheral sidewall.

### Claim 24 (depends on 8)

The three-dimensional memory device of claim 8, wherein the contact well set has an additional vertical cross-sectional profile along an additional vertical plane that is parallel to the second horizontal direction, and wherein the additional vertical cross-sectional profile includes an additional stepwise descending vertical cross-sectional profile as a function of a distance from the first peripheral sidewall toward the second peripheral sidewall along the second horizontal direction, followed by an additional vertical step at one of the first vertical surface and the second vertical surface, and then followed by an additional stepwise ascending vertical cross-sectional profile as a function of the distance from the first peripheral sidewall toward the second peripheral sidewall along the first horizontal direction.

### Claim 25 (depends on 24)

The three-dimensional memory device of claim 24, wherein each horizontal surface within the additional stepwise descending vertical cross-sectional profile is vertically offset from any horizontal surface within the additional stepwise ascending vertical cross-sectional profile by the additional vertical step.

### Claim 26 (depends on 25)

The three-dimensional memory device of claim 25, wherein each of the first vertical surface, the second vertical surface, the third vertical surface, and the fourth vertical surface comprises a respective first vertical edge that coincides with the common vertical line, a respective second vertical edge located within one of the four peripheral sidewalls of the contact well set, an upper stepped edge connecting a top end of the respective first vertical edge and a top end of the respective second vertical edge, and a lower stepped edge connecting a bottom end of the respective first vertical edge and a bottom end of the respective second vertical edge.

### Claim 27 (depends on 26)

The three-dimensional memory device of claim 26, wherein:
a vertical distance between the upper stepped edge of the first vertical surface and the lower stepped edge of first vertical surface is the same as a thickness of a first number of pairs of insulating layers and electrically conductive layers of the alternating stack within the first vertical surface; and
a vertical distance between the upper stepped edge of the second vertical surface and the lower stepped edge of second vertical surface is the same as a thickness of the first number of pairs of insulating layers and electrically conductive layers of the alternating stack within the second vertical surface.

### Claim 28 (depends on 27)

The three-dimensional memory device of claim 27, wherein:
a vertical distance between the upper stepped edge of the third vertical surface and the lower stepped edge of third vertical surface is the same as a thickness of a second number of pairs of insulating layers and electrically conductive layers of the alternating stack within the third vertical surface; and
a vertical distance between the upper stepped edge of the fourth vertical surface and the lower stepped edge of fourth vertical surface is the same as a thickness of the second number of pairs of insulating layers and electrically conductive layers of the alternating stack within the fourth vertical surface.

### Claim 29 (depends on 28)

The three-dimensional memory device of claim 28, wherein the second number is different from the first number.