# US 2019/0319002 A1 · Device, semiconductor package and method of manufacturing semiconductor package

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- Number: US 2019/0319002 A1
- Document ID: US20190319002A1
- Status: Published application
- Kind: A1
- Application number: 16/129,736
- Filed: 2018-09-12
- Published: 2019-10-17
- Earliest claimed: 2018-04-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Kuei Hsu; Ming-Chih Yew; Po-Hao Tsai; Po-Yao Lin; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US20190319002A1

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 72/90: Bond pads, in general
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/655: Fan-out layouts
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

## Claims

### Claim 1

A device, comprising:
a first dielectric layer;
a pad pattern disposed on the first dielectric layer and comprising:
at least one pad portion embedded in the first dielectric layer, wherein a lower surface of the at least one pad portion is substantially coplanar with a lower surface of the first dielectric layer; and
a peripheral portion surrounding the at least one pad portion; and
a second dielectric layer disposed on the pad pattern and comprising a plurality of extending portions extending through the peripheral portion.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein the peripheral portion is disposed on an upper surface of the first dielectric layer, and the at least one pad portion is connected to the peripheral portion, and extends from the upper surface to the lower surface of the first dielectric layer.

### Claim 3 (depends on 1)

The device as claimed in claim 1, wherein the at least one pad portion and the peripheral portion are integrally formed.

### Claim 4 (depends on 1)

The device as claimed in claim 1, wherein a sum of layout areas of the plurality of extending portions is substantially 3% to 60% of a sum of layout areas of the at least one pad portion and the peripheral portion.

### Claim 5 (depends on 1)

The device as claimed in claim 1, wherein the plurality of extending portions surround a periphery of the at least one pad portion.

### Claim 6 (depends on 1)

The device as claimed in claim 1, wherein the at least one pad portion comprises a plurality of pad portions embedded in the first dielectric layer, the peripheral portion surrounds the plurality of pad portions, and the plurality of extending portions surround each of the plurality of pad portions.

### Claim 7 (depends on 1)

The device as claimed in claim 1, wherein the pad portion comprises a plurality of pad recesses extending through the at least one pad portion, and the plurality of extending portions surround a periphery of the at least one pad portion.

### Claim 8

A semiconductor package, comprising:
an encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material; and
a redistribution structure extended over the encapsulated semiconductor device and electrically connected to the semiconductor device, wherein the redistribution structure comprises:
a dielectric layer;
a pad pattern disposed on the dielectric layer, wherein pad pattern comprises at least one pad portion embedded in the dielectric layer, and a lower surface of the pad pattern is substantially coplanar with a lower surface of the dielectric layer away from the encapsulated semiconductor device; and
a plurality of dielectric plugs extending through the pad pattern and surrounding the at least one pad portion.

### Claim 9 (depends on 8)

The semiconductor package as claimed in claim 8, wherein the pad pattern further comprises a peripheral portion surrounding the at least one pad portion, and the plurality of dielectric plugs extend through the peripheral portion.

### Claim 10 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the peripheral portion is disposed on an upper surface of the dielectric layer, the at least one pad portion extends from the upper surface to the lower surface of the dielectric layer, and a lower surface of the at least one pad portion is substantially coplanar with the lower surface of the dielectric layer.

### Claim 11 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the at least one pad portion comprises a plurality of pad portions embedded in the dielectric layer, and the plurality of dielectric plugs surround a periphery of the plurality of pad portions.

### Claim 12 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the at least one pad portion comprises a plurality of pad portions, and the plurality of dielectric plugs surround each of the plurality of pad portions.

### Claim 13 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the pad portion comprises a plurality of pad recesses extending through the at least one pad portion, and the plurality of dielectric plugs surround a periphery of the at least one pad portion.

### Claim 14 (depends on 8)

The semiconductor package as claimed in claim 8, further comprising an electrical component mounted on the lower surface of the pad pattern.

### Claim 15 (depends on 14)

The semiconductor package as claimed in claim 14, wherein the electrical component comprises an electrical connector bump or a passive device.

### Claim 16 (depends on 8)

The semiconductor package as claimed in claim 8, wherein the encapsulated semiconductor device further comprising:
a plurality of conductive joints disposed around the semiconductor device; and
a substrate disposed over the semiconductor device through the conductive joints, wherein the encapsulating material encapsulates the conductive joints.

### Claim 17

A method of manufacturing a semiconductor package, comprising:
forming a redistribution structure on a carrier, wherein forming the redistribution structure on the carrier comprises:
forming a first dielectric layer on the carrier, wherein the first dielectric layer comprises a pad opening;
forming a pad pattern on the first dielectric layer, wherein the pad pattern extends into the pad opening and comprises a plurality of holes surrounding the pad opening; and
forming a second dielectric layer on the pad pattern, wherein the second dielectric layer fills the plurality of holes;
forming an encapsulated semiconductor device on the redistribution structure; and
removing the carrier to reveal a lower surface of the pad pattern.

### Claim 18 (depends on 17)

The method of manufacturing the semiconductor package as claimed in claim 17, further comprising:
mounting an electrical component on the lower surface of the pad pattern.

### Claim 19 (depends on 17)

The method of manufacturing the semiconductor package as claimed in claim 17, wherein forming the encapsulated semiconductor device on the redistribution structure comprises:
disposing a semiconductor device on the redistribution structure; and
forming an encapsulating material on the redistribution structure to encapsulate the semiconductor device.

### Claim 20 (depends on 19)

The method of manufacturing the semiconductor package as claimed in claim 19, wherein forming the encapsulated semiconductor device on the redistribution structure comprises:
mounting a substrate over the semiconductor device through a plurality of conductive joints before the encapsulating material is formed on the redistribution structure, wherein the encapsulating material encapsulates the conductive joints.