# US 2019/0318995 A1 · Semiconductor Wafer, Semiconductor Chip and Method of Fabricating a Semiconductor Wafer

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- Number: US 2019/0318995 A1
- Document ID: US20190318995A1
- Status: Published application
- Kind: A1
- Application number: 16/385,233
- Filed: 2019-04-16
- Published: 2019-10-17
- Earliest claimed: 2018-04-17
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Oliver Blank
- Web page: https://patentgrep.com/patent/US20190318995A1

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 46/503: {Located in scribe lines}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten.

## Claims

### Claim 1

A semiconductor wafer, comprising:
a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions, the component positions comprising an active device structure; and
an auxiliary structure positioned in one or more of the scribe line regions,
wherein the auxiliary structure is electrically coupled to an auxiliary contact pad comprising tungsten,
wherein the auxiliary contact pad has an exposed tungsten surface.

### Claim 2 (depends on 1)

The semiconductor wafer of claim 1, wherein the auxiliary contact pad has a thickness in a range of 50 nm to 1000 nm.

### Claim 3 (depends on 1)

The semiconductor wafer of claim 1, wherein the auxiliary contact pad is positioned in a scribe line region.

### Claim 4 (depends on 1)

The semiconductor wafer of claim 1, wherein the auxiliary contact pad is substantially coplanar with a first conductive layer of a metallization structure that is positioned on, and electrically coupled with, the active device structure in the component positions.

### Claim 5 (depends on 4)

The semiconductor wafer of claim 4, wherein the metallization structure further comprises a second conductive layer that is positioned in the component positions, and wherein the scribe line regions are free of the second conductive layer.

### Claim 6 (depends on 1)

The semiconductor wafer of claim 1, wherein the auxiliary structure and the active device structure each include a transistor device structure comprising a cell region that is laterally surrounded by an edge termination region.

### Claim 7 (depends on 6)

The semiconductor wafer of claim 6, wherein the cell region comprises a semiconductor layer of a first conductivity type forming a drift region, a body region of a second conductivity type that opposes the first conductivity type on the drift region, a source region of the first conductivity type on the body region, and a plurality of trenches, each trench comprising at least one of a field plate and a gate electrode.

### Claim 8 (depends on 7)

The semiconductor wafer of claim 7, wherein the plurality trenches comprises a plurality of columnar trenches, each columnar trench comprising a field plate and a plurality of elongated trenches, each elongated trench comprising a gate electrode.

### Claim 9 (depends on 8)

The semiconductor wafer of claim 8, wherein the transistor device structure further comprises one or more insulation layers arranged on the elongated trenches and on the source region, and a tungsten plug extending through the one or more insulation layers and arranged on the field plate, and wherein a first conductive layer of a metallization structure that is positioned on, and electrically coupled with, the active device structure in the component positions is arranged on the tungsten plug and is electrically coupled to the source region and the body region.

### Claim 10

A method of fabricating a semiconductor wafer, the method comprising:
providing a semiconductor wafer;
forming active device structures in component positions with scribe line regions located at least one of adjacent to and between the component positions;
forming one or more auxiliary structures in one or more of the scribe line regions;
forming a metallization structure on the component positions and on the scribe line regions, wherein a first conductive layer of the metallization structure comprises tungsten;
forming one or more auxiliary contact pads in the tungsten layer arranged in the scribe line regions and that are electrically coupled to the one or more auxiliary structures.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a second conductive layer of the metallization structure, the second conductive layer being positioned on the component positions and leaving the one or more auxiliary contact pads in the scribe lines exposed, wherein the second conductive layer is tungsten free.

### Claim 12 (depends on 10)

The method of claim 10, wherein at least one of forming the one or more auxiliary structures and forming the active device structures comprises:
forming a body region of a second conductivity type that opposes a first conductivity type in a semiconductor layer of the first conductivity type forming a drift region;
forming a source region of the first conductivity type on the body region;
forming a plurality of columnar trenches;
forming a field plate in each columnar trench;
forming an elongated trench in regions of the semiconductor layer between the columnar trenches;
forming a gate electrode in the elongated trench;
forming one or more insulation layers arranged on the columnar trenches, the elongated trench and on the source region;
forming an opening in the one or more insulation layers above the field plate; and
inserting tungsten into the opening and onto the field plate,
wherein the first conductive layer is formed on the tungsten in the opening to electrically couple the first conductive layer to the source region and body region.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
applying an external contact to the one or more auxiliary contact pads; and
measuring one or more parameters of the one or more auxiliary structures.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
singulating the semiconductor wafer by cutting along the scribe line regions and through the one or more auxiliary structures and the one or more auxiliary contact pads.

### Claim 15

A semiconductor chip, comprising:
a semiconductor substrate comprising an active device region and a peripheral edge region laterally surrounding the active device region,
wherein a discrete region of a layer comprising tungsten is arranged in the peripheral edge region.