# US 2019/0318994 A1 · Semiconductor package using cavity substrate and manufacturing methods

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0318994 A1
- Document ID: US20190318994A1
- Status: Published application
- Kind: A1
- Application number: 15/953,591
- Filed: 2018-04-16
- Published: 2019-10-17
- Earliest claimed: 2018-04-16
- Assignees: Amkor Technology, Inc.
- Applicants: Amkor Technology, Inc.
- Inventors: Young Do Kweon; JeongByung Chae; DongJoo Park; ByoungWoo Cho; SeHwan Hong
- Web page: https://patentgrep.com/patent/US20190318994A1

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/688: {Flexible insulating substrates}
- H10W 72/0198: {batch processes}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07353: {changes in shapes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.

## Claims

### Claim 1

A semiconductor package, comprising:
a cavity substrate including:
a redistribution structure comprising a redistribution structure upper surface having a plurality of pads, a redistribution structure lower surface opposite the redistribution structure upper surface, and one or more redistribution structure sidewalls adjacent the redistribution structure upper surface and the redistribution structure lower surface; and
a cavity layer on the redistribution structure upper surface, the cavity layer comprising a cavity layer upper surface, a cavity layer lower surface opposite the cavity layer upper surface, one or more cavity layer sidewalls adjacent the cavity layer upper surface and the cavity layer lower surface, and a cavity in the cavity layer upper surface that exposes one or more pads of the plurality of pads;
a semiconductor die in the cavity of the cavity layer, the semiconductor die comprising a semiconductor die first surface, a semiconductor die second surface opposite the semiconductor die first surface, one or more semiconductor die sidewalls adjacent the semiconductor die first surface and the semiconductor die second surface, and a plurality of conductive structures along the semiconductor die second surface that are operatively coupled to integrated circuitry of the semiconductor die; and
an encapsulant that encapsulates the semiconductor die in the cavity of the cavity layer and that covers the one or more redistribution structure sidewalls.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, comprising:
a trench that passes through a cavity layer sidewall from the one or more cavity layer sidewalls;
wherein the encapsulant layer further fills the trench.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution structure lower surface comprises a plurality of external connection structures that are electrically connected to the plurality of pads.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, further comprising an underfill material between the semiconductor die second surface the redistribution structure upper surface.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising:
a second cavity substrate over the cavity substrate, the second cavity substrate includes an interposer and a second cavity layer having a second cavity; and
wherein the semiconductor die is further in the second cavity.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the encapsulant layer fills a gap between the semiconductor die second surface and the redistribution structure upper surface.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising a plurality of conductive interconnect structures that pass through the cavity layer and between the cavity layer upper surface and the cavity layer lower surface and that are physically and electrically connected to pads from the plurality of pads.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, further comprising:
a semiconductor package comprising a semiconductor package upper surface, a semiconductor package lower surface opposite the semiconductor package upper surface, and a plurality of second external connection structures along the semiconductor package lower surface;
wherein the plurality of second external connection structures are physically and electrically connected to upper surfaces of the plurality of conductive interconnect structures.

### Claim 9 (depends on 7)

The semiconductor package of claim 7, further comprising an interposer on the cavity layer upper surface, the interposer comprising a plurality of second pads on an upper surface of the interposer.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, further comprising:
a semiconductor package comprising a semiconductor package upper surface, a semiconductor package lower surface opposite the semiconductor package upper surface, and a plurality of second external connection structures along the semiconductor package lower surface;
wherein the plurality of second external connection structures are physically and electrically connected to the plurality of second pads.

### Claim 11

A semiconductor package, comprising:
a cavity substrate including:
a redistribution structure comprising a redistribution structure upper surface having a plurality of pads, a redistribution structure lower surface opposite the redistribution structure upper surface, and one or more redistribution structure sidewalls adjacent the redistribution structure upper surface and the redistribution structure lower surface; and
a cavity layer on the redistribution structure upper surface, the cavity layer comprising a cavity layer upper surface, a cavity layer lower surface opposite the cavity layer upper surface, one or more cavity layer sidewalls adjacent the cavity layer upper surface and the cavity layer lower surface, a cavity in the cavity layer upper surface that exposes one or more pads from the plurality of pads, and a trench that passes through a cavity layer sidewall from the one or more cavity layer sidewalls;
a semiconductor die in the cavity of the cavity layer, the semiconductor die comprising a semiconductor die first surface, a semiconductor die second surface opposite the semiconductor die first surface, one or more semiconductor die sidewalls adjacent the semiconductor die first surface and the semiconductor die second surface, and a plurality of conductive structures along the semiconductor die second surface that are operatively coupled to integrated circuitry of the semiconductor die; and
an encapsulant that encapsulates the semiconductor die in the cavity of the cavity layer and fills the trench.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein the redistribution structure lower surface comprises a plurality of external connection structures that are electrically connected to the plurality of pads.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, further comprising:
an underfill material between the semiconductor die second surface the redistribution structure upper surface;
wherein the encapsulant layer further encapsulates the underfill material.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, wherein the encapsulant layer fills a gap between the semiconductor die second surface and the redistribution structure upper surface.

### Claim 15 (depends on 1)

The semiconductor package of claim 1, further comprising:
a plurality of conductive interconnect structures that pass through the cavity layer and between the cavity layer upper surface and the cavity layer lower surface and that are physically and electrically connected to pads from the plurality of pads; and
a semiconductor package comprising a plurality of second external connection structures that are physically and electrically connected to the plurality of conductive interconnect structures.

### Claim 16 (depends on 11)

The semiconductor package of claim 11, further comprising:
a plurality of conductive interconnect structures that pass through the cavity layer and between the cavity layer upper surface and the cavity layer lower surface and that are physically and electrically connected to pads from the plurality of pads;
an interposer on the cavity layer upper surface, the interposer comprising a plurality of second pads on an upper surface of the interposer; and
a semiconductor package comprising a plurality of second external connection structures that are physically and electrically connected to the plurality of second pads.

### Claim 17

A method of fabricating a plurality of semiconductor packages, the method comprising:
placing a plurality of semiconductor dies in a plurality of cavity substrates;
attaching attachment structures of each semiconductor die to a plurality of pads of a redistribution structure that are exposed by a cavity of each cavity substrate; and
encapsulating, via an encapsulating material, the plurality of semiconductor dies in the plurality of cavity substrates.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
each cavity comprises a trench in a sidewall of the cavity; and
said encapsulating comprises filling the trench in the sidewall of each cavity.

### Claim 19 (depends on 17)

The method of claim 17, wherein said encapsulating comprises covering a sidewall of the redistribution structure for each cavity substrate.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
stacking semiconductor package over the encapsulated semiconductor die; and
electrically connecting the semiconductor package to the redistribution structure of each cavity substrate.