# US 2019/0318990 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318990 A1 - Document ID: US20190318990A1 - Status: Published application - Kind: A1 - Application number: 16/370,370 - Filed: 2019-03-29 - Published: 2019-10-17 - Earliest claimed: 2018-04-16 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kazuyuki NAKAGAWA; Shinji BABA; Hiroshi KOIZUMI - Web page: https://patentgrep.com/patent/US20190318990A1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 20/4421: {the principal metal being copper} - H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) - H10W 40/10: Arrangements for heating - H10W 72/00: Interconnections or connectors in packages - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/30: Die-attach connectors - H10W 72/851: {Dispositions of multiple connectors or interconnections} - H10W 72/90: Bond pads, in general - H10W 20/43: Layouts of interconnections - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 72/07236: {Soldering or alloying} - H10W 72/07252: {changes in structures or sizes} - H10W 72/221: {Structures or relative sizes} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/354: {comprising polymers} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor chip including a first front surface, a first back surface on an opposite side from the first front surface, and a plurality of electrodes arrayed on the first front surface; and a wiring substrate including a first main surface on which the semiconductor chip is mounted, a second main surface on an opposite side from the first main surface, a plurality of pads arrayed on the first main surface, and a plurality of wiring layers provided between the first main surface and the second main surface, wherein the plurality of electrodes of the semiconductor chip and the plurality of pads of the wiring substrate face each other and are electrically connected through conductive members, wherein the wiring substrate includes a pad forming layer in which the plurality of pads is formed and a first wiring layer which is located at a position closer to the pad forming layer than the other wiring layers, wherein the plurality of pads includes a first pad and a second pad, wherein the first wiring layer includes a first via land, a second via land, a first wiring and a second wiring, wherein the first via land is arranged at a position overlapping with the first pad in plan view and electrically connected to the first pad through a first via, wherein the second via land is arranged at a position overlapping with the second pad in plan view and electrically connected to the second pad through a second via, wherein the first wiring is connected to the first via land and extends in a first direction and the second wiring is connected to the second via land and extends adjacent to the first wiring in the first direction, wherein, in a second direction intersecting with the first direction, a width of the first via land is larger than a width of the first wiring, and wherein the second wiring is adjacent to the first via land and overlaps with the first pad in plan view. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first main surface of the wiring substrate and each of the plurality of wiring layers include a first region overlapping with the semiconductor chip and a second region located around the first region without overlapping with the semiconductor chip, wherein the first and second wirings extend across the first region and the second region, wherein the first pad configured to receive transmission of a first signal and the second pad configured to receive transmission of a second signal different from the first signal, and wherein the first wiring layer which is located at a position closest to the pad forming layer among the plurality of wiring layers. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the first via land has a first width in the first direction and a second width in the second direction in plan view, wherein the second width of the first via land is smaller than the first width, and wherein, in a region where the first pad and the second wiring overlap, a width of the second wiring in the second direction is smaller than the second width of the first via land. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the first via has a third width in the first direction and a fourth width in the second direction in plan view, wherein the fourth width of the first via is smaller than the third width, wherein the second width of the first via land is larger than the fourth width of the first via, and wherein the first width of the first via land is larger than the third width of the first via. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the plurality of pads includes a plurality of first potential pads configured to receive a supply of a first potential, wherein the plurality of conductor patterns includes first conductor patterns electrically connected respectively to the plurality of first potential pads through a plurality of first potential vias, wherein each of the plurality of first potential vias has a fifth width in the second direction in plan view, and wherein the fifth width of each of the plurality of first potential vias is larger than the fourth width of the first via. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the first wiring is arranged on one side of the first via land and the first conductor pattern is arranged on the other side of the first via land in the first direction, and wherein the second via land is arranged between the first via land and the first conductor pattern in the first direction. ### Claim 7 (depends on 4) The semiconductor device according to claim 4, wherein the plurality of first potential pads is arrayed along a third direction intersecting the first direction. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the wiring substrate includes a second wiring layer located at a position closest to the first wiring layer among the plurality of wiring layers, wherein the second wiring layer includes a second conductor pattern electrically connected to the first conductor pattern and having a larger area than a portion of the first conductor pattern in the first region, and wherein each of the plurality of first-layer wirings overlaps with the second conductor pattern in the second wiring layer in the second region. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the first conductor pattern configured to receive a supply of the first potential is located both in the first region and in the second region in the first wiring layer, and wherein the first conductor pattern separated from each of the plurality of first-layer wirings is arranged between the plurality of first-layer wirings in the second region. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the pad forming layer includes a third conductor pattern arranged in the second region, configured to receive a supply of the first potential, and having an area larger than a portion of the first conductor pattern in the first region, and wherein each of the plurality of first-layer wirings overlaps with the third conductor pattern in the pad forming layer in the second region. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the plurality of first-layer wirings and the plurality of conductor patterns are covered with a first insulating film, wherein the third conductor pattern in the second region is covered with a second insulating film different from the first insulating film, and wherein the second insulating film is not formed in the first region and the plurality of pads are exposed from the second insulating film. ### Claim 12 (depends on 3) The semiconductor device according to claim 3, wherein the wiring substrate includes a second wiring layer located at a position closest to the first wiring layer among the plurality of wiring layers, wherein, in the first wiring layer, one end of the first wiring is connected to the first via land, and the other end of the first wiring is connected to a fourth conductor pattern, wherein the fourth conductor pattern is connected to a first signal via configured to electrically connect the first wiring layer and the second wiring layer, and wherein a width of the fourth conductor pattern in the second direction is larger than the second width of the first via land. ### Claim 13 (depends on 4) The semiconductor device according to claim 4, wherein the wiring substrate includes a second wiring layer located at a position closest to the first wiring layer among the plurality of wiring layers, wherein a plurality of pads arranged in the pad forming layer include a plurality of signal pads configured to receive transmission of a signal, wherein the plurality of conductor patterns formed in the first wiring layer are arranged at positions overlapping with the plurality of signal pads and include a plurality of signal via lands electrically connected to the plurality of signal pads, wherein the plurality of signal via lands are connected respectively to the plurality of signal vias configured to electrically connect the first wiring layer and the second wiring layer through the plurality of first-layer wirings, and the plurality of signal via lands do not overlap with the plurality of signal vias. ### Claim 14 (depends on 4) The semiconductor device according to claim 4, wherein the plurality of first-layer wirings and the plurality of conductor patterns are covered with a first insulating film made of a photosensitive resin, wherein a plurality of through holes formed at positions overlapping with the plurality of conductor patterns are formed in the first insulating film, and wherein the plurality of vias are embedded in the plurality of through holes. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the wiring substrate includes a second wiring layer located at a position closest to the first wiring layer among the plurality of wiring layers, wherein the wiring substrate includes a third insulating film between the first wiring layer and the second wiring layer, and wherein a thickness of the first insulating film is smaller than a thickness of the third insulating film. ### Claim 16 (depends on 2) The semiconductor device according to claim 2, wherein the conductive members configured to electrically connect the plurality of electrodes of the semiconductor chip and the plurality of pads of the wiring substrate are sealed with an insulative resin, and wherein each of side surfaces of the plurality of pads comes into contact with the insulative resin or each of the conductive members. ### Claim 17 (depends on 4) The semiconductor device according to claim 4, wherein the plurality of pads includes a third pad configured to receive a third signal different from the first signal and the second signal, wherein the plurality of conductor patterns formed in the first wiring layer include a third via land arranged at a position overlapping with the third pad in plan view and electrically connected to the third pad through a third via, and wherein the plurality of first-layer wirings include a third wiring connected to the third via land and extending adjacent to the first wiring in the first direction, and wherein, in plan view, the first via land is located between the second wiring and the third wiring, and the third wiring overlaps with the first pad. ### Claim 18 (depends on 4) The semiconductor device according to claim 4, wherein the plurality of pads includes a fourth pad arrayed adjacent to the first pad along a second direction intersecting the first direction and configured to receive transmission of a fourth signal different from the first signal and the second signal, wherein the plurality of conductor patterns formed in the first wiring layer include a fourth via land arranged at a position overlapping with the fourth pad in plan view and electrically connected to the fourth pad through a fourth via, and wherein five or more of the plurality of first-layer wirings are arranged between the first via land and the fourth via land in plan view. ### Claim 19 A semiconductor device comprising: a semiconductor chip including a first front surface, a first back surface opposite the first front surface, and a plurality of electrodes arrayed on the first front surface; and a wiring substrate including a first main surface on which the semiconductor chip is mounted such that the first main surface faces the first front surface of the semiconductor chip, a second main surface opposite the first main surface, a plurality of pads arranged on the first main surface and a plurality of external electrodes arrayed on the second main surface, the wiring substrate including; a first insulating layer arranged between the first main surface and the second main surface, a first wiring layer formed on the first insulating layer and arranged between the first insulating layer and the first main surface, a second insulating layer formed on the first wiring layer and arranged between the first wiring layer and the first main surface, a second wiring layer formed on the second insulating layer and arranged between the second insulating layer and the first main surface, a third insulating layer formed on the second wiring layer and arranged between the second wiring layer and the first main surface, a third wiring layer formed on the third insulating layer and arranged between the third wiring layer and the first main surface, and a fourth insulating layer formed on the third wiring layer and includes the main surface, wherein a distance from the second wiring layer to third wiring layer is smaller than a distance from the first wiring layer to the second wiring layer in a thickness direction of the wiring substrate, and wherein the fourth insulating layer is not overlapped with the semiconductor chip in a plan view. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the first wiring layer includes a first conductive pattern, wherein the second wiring layer includes a wiring for signal, wherein the third wiring layer includes the plurality of pads and a second conductive pattern, wherein the wiring is sandwiched between the first and second conductive patterns in a cross section view, wherein the third conducive pattern is not overlapped with the semiconductor chip and is covered with the fourth insulating layer in the cross section view.