# US 2019/0318989 A1 · Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0318989 A1
- Document ID: US20190318989A1
- Status: Published application
- Kind: A1
- Application number: 15/951,243
- Filed: 2018-04-12
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Dongbing Shao; Lawrence A. Clevenger; Shyng-Tsong Chen; Hao Tang; Jing Sha
- Web page: https://patentgrep.com/patent/US20190318989A1

## CPC

- H10W 20/43: Layouts of interconnections
- H10D 89/10: Integrated device layouts
- H10P 50/73: {using masks for insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

## Claims

### Claim 1

A photolithographic mask, comprising:
at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

### Claim 2 (depends on 1)

The photolithographic mask of claim 1, wherein the compound shape is a shape selected from the group consisting of a T-shape, +-shape, V-shape, and Z-shape.

### Claim 3 (depends on 2)

The photolithographic mask of claim 2, wherein the photolithographic mask is configured to have the at least one merged via pattern above a first metal line in a first metallization layer and over trench templates on a second metallization layer of a back end of line metallization interconnect structure.

### Claim 4 (depends on 3)

The photolithographic mask of claim 3, wherein the merged via pattern is configured to be above at least two predetermined via locations.

### Claim 5 (depends on 3)

The photolithographic mask of claim 3, wherein the merged via pattern is configured to locate one via at an end of the first metal line in the first metallization layer and a second metal line in the second metallization layer without additional enclosure.

### Claim 6

A back end of line metallization interconnect structure, comprising:
a first wire segment in a first metallization layer;
a second wire segment in a second metallization layer, wherein the end of the second wire segment is above the end of the first wire segment, and the first wire segment is orthogonal to the second wire segment;
a third wire segment in the first metallization layer;
a fourth wire segment in the second metallization layer, wherein the end of the fourth wire segment is above the end of the third wire segment, and the third wire segment is orthogonal to the fourth wire segment, and wherein the fourth wire segment is co-linear with the second wire segment;
a fifth wire segment in the first metallization layer; and
a sixth wire segment in the second metallization layer, wherein the end of the sixth wire segment is above the end of the fifth wire segment, and the fifth wire segment is orthogonal to the sixth wire segment, and the fifth wire segment is orthogonal to the first wire segment and the third wire segment.

### Claim 7 (depends on 6)

The back end of line metallization interconnect structure of claim 6, wherein the end of the second wire segment in the second metallization layer does not extend beyond the edge of the end of the first wire segment in the first metallization layer by more than 1.5 nm.

### Claim 8 (depends on 6)

The back end of line metallization interconnect structure of claim 6, further comprising, a first via at the end of the first wire segment extending to the second wire segment, a second via at the end of the third wire segment extending to the fourth wire segment, and a third via extending from the end of the fifth wire segment to the sixth wire segment.

### Claim 9 (depends on 6)

The back end of line metallization interconnect structure of claim 6, further comprising, a seventh wire segment in the first metallization layer and an eighth wire segment in the second metallization layer, wherein the end of the eighth wire segment is above the end of the seventh wire segment, and the eighth wire segment is orthogonal to the seventh wire segment, and wherein the seventh wire segment is co-linear with the fifth wire segment.

### Claim 10 (depends on 9)

The back end of line metallization interconnect structure of claim 9, further comprising, a fourth via at the end of the seventh wire segment extending to the eighth wire segment.

### Claim 11 (depends on 10)

The back end of line metallization interconnect structure of claim 10, further comprising, a dielectric line between each adjacent pair of wire segments in the first metallization layer.

### Claim 12 (depends on 10)

The back end of line metallization interconnect structure of claim 10, further comprising, a substrate including one or more semiconductor devices, wherein the first metallization layer is on the substrate.

### Claim 13

A method of forming a merged via, comprising:
forming a plurality of metal lines in a first metallization layer on a substrate, wherein each adjacent pair of metal lines is separated by a dielectric line;
forming a cap layer on each dielectric line;
forming a dielectric layer on the plurality of metal lines in a first metallization layer and cap layers;
forming a hard mask layer on the dielectric layer;
forming a plurality of trench templates on the hard mask layer;
forming a via mask layer on the plurality of trench templates; and
forming a merged via opening in the via mask layer, wherein the via mask opening includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

### Claim 14 (depends on 13)

The method of claim 13, wherein the compound shape is a shaped selected from the group consisting of a T-shape, +-shape, V-shape, and Z-shape, wherein the compound shape has rounded inside corners, and wherein the rounded inside corners are not located directly above the plurality of metal lines in a first metallization layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising removing a portion of the hard mask layer exposed by the merged via opening and between edges of adjacent trench templates.

### Claim 16 (depends on 15)

The method of claim 15, further comprising removing a portion of the dielectric layer exposed by the removed potion of the hard mask, merged via opening, and between the edges of adjacent trench templates, wherein removing the exposed portion of the dielectric layer forms at least one trench and at least one via opening to at least one of the plurality of metal lines in the first metallization layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising removing the via mask layer and trench templates.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a conductive material in the at least one trench and at least one via opening to form one or more metal lines in the dielectric layer, and one or more vias between at least one of the plurality of metal lines in the first metallization layer and at least one of the one or more metal lines in the dielectric layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the conductive material is copper or cobalt.

### Claim 20 (depends on 19)

The method of claim 19, wherein the substrate includes at least one semiconductor device electrically connected to at least one of the plurality of metal lines in the first metallization layer.