# US 2019/0318986 A1 · Semiconductor Device Having Via Sidewall Adhesion With Encapsulant

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- Number: US 2019/0318986 A1
- Document ID: US20190318986A1
- Status: Published application
- Kind: A1
- Application number: 16/265,291
- Filed: 2019-02-01
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Yun Chen Hsieh; Hui-Jung Tsai; Hung-Jui Kuo
- Web page: https://patentgrep.com/patent/US20190318986A1

## CPC

- H10W 70/635: {Through-vias}
- H10P 14/46: using a liquid
- H10P 50/267: {using plasmas}
- H10P 50/667: {by liquid etching only}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

## Claims

### Claim 1

A method, comprising:
forming a die, the die comprising a pad and a passivation layer over the pad;
forming a first opening through the passivation layer;
depositing a resist layer over the die;
patterning the resist layer to form a second opening aligned to the first opening;
forming a via in the second opening, the via having a first co-efficient of thermal expansion (CTE);
forming a solder cap on the via, wherein a first material of the solder cap flows to a sidewall of the via; and
encapsulating the via in a first encapsulant, wherein the first encapsulant has a second CTE and a curing temperature, wherein a ratio of the second CTE and first CTE is less than 2.5:1 or the first curing temperature is less than 250° C.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
prior to encapsulating the via, singulating the die from a wafer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
after encapsulating the via, singulating the die from a wafer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
prior to encapsulating the via, etching the solder cap to remove the first material from the sidewall of the via.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
testing the die by probing the solder cap.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the via comprises plating a conductive material, and wherein forming the solder cap comprises plating the first material over the conductive material.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
attaching the die to a carrier; and
laterally encapsulating the die by a second encapsulant, where a material of the second encapsulant is different than a material of the first encapsulant.

### Claim 8

A method, comprising:
disposing a metal pillar over and coupled to a contact pad of a die, the metal pillar comprising a first material;
forming a solder cap over the metal pillar, the solder cap comprising a second material;
etching the solder cap, wherein the etching uses an etchant having selectivity between second material and the first material; and
attaching the die to a carrier.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
testing the die by probing the solder cap.

### Claim 10 (depends on 8)

The method of claim 8, wherein the etching is a wet etch process.

### Claim 11 (depends on 8)

The method of claim 8, wherein the etching is a plasma etch process.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
encapsulating the metal pillar with a first encapsulant after etching the solder cap.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first encapsulant is a polymer or molding compound, the first encapsulant having a first co-efficient of thermal expansion (CTE) between 8 ppm/° C. and 40 ppm/° C.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
curing the first encapsulant at a temperature of 250° C. or less.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
prior to encapsulating the metal pillar, singulating the die from a wafer; and
attaching the die to a carrier.

### Claim 16 (depends on 12)

The method of claim 12, further comprising:
after encapsulating the metal pillar, singulating the die from a wafer;
attaching the die to a carrier; and
encapsulating the die with a second encapsulant.

### Claim 17

A package, comprising:
an embedded die having a contact pad formed at an active side thereof;
a metal via disposed over the contact pad; and
a first encapsulant laterally encapsulating the metal via, wherein the first encapsulant contacts the sidewall of the metal via, wherein an interface between the sidewall of the metal via and the first encapsulant is free of tin adjacent to a top surface of the metal via.

### Claim 18 (depends on 17)

The package of claim 17, wherein the first encapsulant comprises a first material having a first co-efficient of thermal expansion (CTE), wherein the metal via comprises a second material having a second CTE, wherein a ratio of the first CTE to the second CTE is between 0.5:1 and 2.5:1.

### Claim 19 (depends on 17)

The package of claim 17, wherein the first encapsulant has a curing temperature of 250° C. or less.

### Claim 20 (depends on 17)

The package of claim 17, wherein the first encapsulant is disposed within the lateral extents of the embedded die, wherein the embedded die is laterally encapsulated by a second encapsulant.