# US 2019/0318985 A1 · Package structure for electronic assemblies > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318985 A1 - Document ID: US20190318985A1 - Status: Published application - Kind: A1 - Application number: 16/006,041 - Filed: 2018-06-12 - Published: 2019-10-17 - Earliest claimed: 2018-04-17 - Assignees: National Taiwan Normal University - Applicants: National Taiwan Normal University - Inventors: Jung-Hsuan CHEN - Web page: https://patentgrep.com/patent/US20190318985A1 ## CPC - H10W 70/635: {Through-vias} - H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass} - H05K 1/0313: {Organic insulating material} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/144: {Stacked arrangements of planar printed circuit boards} - H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/692: Ceramics or glasses - H10W 70/695: Organic materials - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H05K 2201/0116: Porous, e.g. foam - H05K 2201/0154: Polyimide - H05K 2201/041: Stacked PCBs, i.e. having neither an empty space nor mounted components in between - H05K 2201/042: Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other - H05K 2201/10378: Interposers - H05K 2201/10545: Related components mounted on both sides of the PCB - H05K 2201/10734: Ball grid array [BGA]; Bump grid array - H10W 72/072: {of bump connectors} - H10W 72/07253: {changes in shapes} - H10W 72/07254: {changes in dispositions} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A package structure for electronic assemblies includes a porous insulation substrate, a conductive material, a first electronic assembly, and a second electronic assembly. The porous insulation substrate is penetrated with a plurality of through holes, and each of the plurality of through holes has a diameter which is larger than 0 and less than 1 um. The conductive material fills the plurality of through holes. The first electronic assembly is arranged under the porous insulation substrate and electrically connected to the conductive material in the plurality of through holes through at least one first conductive bump. The second electronic assembly is arranged over the porous insulation substrate and electrically connected to the conductive material in the plurality of through holes through at least one second conductive bump to electrically connect to the first electronic assembly. ## Claims ### Claim 1 A package structure for electronic assemblies comprising: a porous insulation substrate penetrated with a plurality of through holes, and each of the plurality of through holes has a diameter which is larger than 0 and less than 1 um and each of the plurality of through holes is arranged in the porous insulation substrate at a same height; a conductive material filling the plurality of through holes; a first electronic assembly arranged under the porous insulation substrate and electrically connected to the conductive material in the plurality of through holes through at least one first conductive bump; and a second electronic assembly arranged over the porous insulation substrate and electrically connected to the conductive material in the plurality of through holes through at least one second conductive bump to electrically connect to the first electronic assembly, wherein the at least one first conductive bump further comprises a plurality of first conductive bumps, and each of the plurality of first conductive bumps is electrically connected to the conductive material in several hundreds of the plurality of through holes, and wherein the at least one second conductive bump further comprises a plurality of second conductive bumps, and each of the plurality of second conductive bumps is electrically connected to the conductive material in several hundreds of the plurality of through holes wherein each of the plurality of first conductive bumps and each of the plurality of second conductive bumps respectively cover at least two of the plurality of through holes. ### Claim 2 (depends on 1) The package structure for electronic assemblies according to claim 1, wherein the conductive material comprises solder. ### Claim 3 (depends on 2) The package structure for electronic assemblies according to claim 2, wherein the solder comprises a tin-included metal with a low melting point, a tin-included alloy, or a metallic composite material including tin. ### Claim 4 (depends on 1) The package structure for electronic assemblies according to claim 1, wherein the at least one first conductive bump and the at least one second conductive bump have shapes of squares or circles. ### Claim 5 (depends on 1) The package structure for electronic assemblies according to claim 1, wherein the at least one first conductive bump and the at least one second conductive bump comprise copper, aluminum, nickel, or a tin-included metal with a low melting point. ### Claim 6 (depends on 1) The package structure for electronic assemblies according to claim 1, wherein the plurality of through holes further comprise several hundreds of through holes. ### Claim 7 (canceled) ### Claim 8 (canceled) ### Claim 9 (depends on 1) The package structure for electronic assemblies according to claim 1, wherein the porous insulation substrate comprises aluminum oxide, silicon dioxide, poly (methyl methacrylate) (PMMA), polycarbonate (PC), or polyimide (PI). ### Claim 10 (depends on 1) The package structure for electronic assemblies according to claim 1, wherein the first electronic assembly or the second electronic assembly is selected from a printed circuit board, an interposer, or an electronic chip.