# US 2019/0318963 A1 · High threshold voltage fet with the same fin height as regular threshold voltage vertical fet

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- Number: US 2019/0318963 A1
- Document ID: US20190318963A1
- Status: Published application
- Kind: A1
- Application number: 15/951,355
- Filed: 2018-04-12
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Xin MIAO; Kangguo CHENG; Chen ZHANG; Wenyu XU
- Web page: https://patentgrep.com/patent/US20190318963A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/837: {comprising vertical IGFETs}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/28: of insulating materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the second vertical fin has a hardmask on top, and wherein the first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region;
reducing the first gate stack to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask;
removing the hardmask; and
forming a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.

### Claim 2 (depends on 1)

The method of claim 1 further comprising forming a first top spacer on the first gate stack and the second gate stack.

### Claim 3 (depends on 1)

The method of claim 1 further comprising doping a first upper portion of the first vertical fin and a second upper portion of the second vertical fin subsequent to forming a first top spacer on the first and second gate stacks.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first top S/D region is epitaxially grown from the first upper portion and the second top S/D region is epitaxially grown from the second upper portion.

### Claim 5 (depends on 3)

The method of claim 3 further comprising forming a second top spacer on the first top spacer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first and second upper portions extend above the first and second top spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first vertical fin and the second vertical fin are substantially a same fin length.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first gate stack and the second gate stack comprise a high-k dielectric material and at least one gate metal.

### Claim 9 (depends on 1)

The method of claim 1 further comprising forming a first vertical transistor and a second vertical transistor;
wherein the first vertical transistor includes the first vertical fin and the first gate stack and the second vertical transistor includes the second vertical fin and the second gate stack.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second vertical transistor has a higher threshold voltage than the first vertical transistor defined by the second gate length being greater than the first gate length.

### Claim 11 (depends on 9)

The method of claim 9, wherein the second gate length being greater than the first gate length results in the second vertical transistor having a lower leakage current than the first vertical transistor.

### Claim 12

A semiconductor device comprising:
a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the first vertical fin and the second vertical fin are substantially a same fin length, wherein the first gate stack has a first gate length and the second gate stack has a second gate length, the second gate length being greater than the first gate length;
a bi-layer top spacer formed on top of the first and second gate stacks;
a first bottom S/D directly on sides of the first vertical fin and a second bottom S/D region directly on sides of the second vertical fin; and
a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the bi-layer top spacer comprises a first top spacer and a second top spacer formed on the first top spacer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first and second top spacers comprise different materials.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein a first epitaxial cap is on top of the first top S/D region and a second epitaxial cap is on top of the second top S/D region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first and second epitaxial caps are different lengths.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, wherein top surfaces of the first top S/D region and the second top S/D region are at different heights.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, wherein a first vertical transistor includes the first vertical fin and the first gate stack and a second vertical transistor includes the second vertical fin and the second gate stack.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the second gate length being greater than the first gate length results in the second vertical transistor having a lower leakage current than the first vertical transistor.

### Claim 20

A method of forming a semiconductor device, the method comprising:
forming a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the first vertical fin and the second vertical fin are substantially a same fin length, wherein the first gate stack has a first gate length and the second gate stack has a second gate length, the second gate length being greater than the first gate length;
forming a bi-layer top spacer on top of the first and second gate stacks;
forming a first bottom S/D region directly on sides of the first vertical fin and a second bottom S/D region directly on sides of the second vertical fin; and
forming a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.