# US 2019/0318948 A1 · Wafer-level inspection using on-valve inspection detectors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318948 A1 - Document ID: US20190318948A1 - Status: Published application - Kind: A1 - Application number: 15/951,578 - Filed: 2018-04-12 - Published: 2019-10-17 - Earliest claimed: 2018-04-12 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Mu-Lung CHE; Chen-Feng HSU - Web page: https://patentgrep.com/patent/US20190318948A1 ## CPC - H10P 72/0616: {Monitoring of warpages, curvatures, damages, defects or the like} - H10P 72/3306: {Horizontal transfer of a single workpiece} - G06T 7/0004: {Industrial image inspection} - G06T 7/001: {using an image reference approach} - H10P 72/0464: {characterised by the construction of the transfer chamber} - H10P 72/3302: {Mechanical parts of transfer devices} - G06T 2207/30148: Semiconductor; IC; Wafer - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract A system and method for wafer-level inspection using on-valve inspection detectors to detect defects on a semiconductor wafer surfaces during a semiconductor device manufacturing process is disclosed herein. In some exemplary embodiments, a method for wafer-level inspection includes: transporting a semiconductor wafer through a transfer port of a processing chamber; scanning a surface of the semiconductor wafer automatically using at least one on-valve inspection detector arranged on a vacuum valve providing access through the transfer port; generating at least one surface image of the surface of the semiconductor wafer; and analyzing the at least one surface image to detect defects on the surface of the semiconductor wafer. ## Claims ### Claim 1 A method for wafer-level inspection comprising: transporting a semiconductor wafer through a transfer port of a processing chamber; scanning a surface of the semiconductor wafer automatically using at least one on-valve inspection detector arranged on a vacuum valve, providing access through the transfer port; generating at least one surface image of the surface of the semiconductor wafer; and analyzing the at least one surface image to detect defects on the surface of the semiconductor wafer. ### Claim 2 (depends on 1) The method of claim 1, wherein the transporting comprises using a transfer mechanism to transport the semiconductor wafer through the transfer port of the processing chamber. ### Claim 3 (depends on 2) The method of claim 2, wherein the transfer mechanism is coupled to a wafer holder for holding the semiconductor wafer and exposing the surface of the semiconductor wafer. ### Claim 4 (depends on 1) The method of claim 1, wherein the at least one on-valve inspection detector comprises a line scan camera. ### Claim 5 (depends on 1) The method of claim 1, wherein the at least one on-valve inspection detector is configured to scan the surface of the semiconductor wafer one pixel line at a time. ### Claim 6 (depends on 1) The method of claim 1, wherein the generating at least one surface image further comprises: transmitting a plurality of line images from the at least one on-valve inspection detector to a local computer; and preprocessing the plurality of line images by the local computer to generate the at least one surface image. ### Claim 7 (depends on 1) The method of claim 1, further comprising: transmitting the at least one surface image to a remote computer; analyzing the at least one surface image by the remote computer; and comparing the at least one surface image to a set of predefined criteria to detect defects on the surface of the semiconductor wafer. ### Claim 8 A wafer-level inspection system comprising: a transfer mechanism configured to automatically transfer a semiconductor wafer through a transfer port of a processing chamber; at least one on-valve inspection detector arranged on a vacuum valve, providing access through the transfer port of the processing chamber, wherein the at least one on-valve inspection detector is configured to scan a surface of the semiconductor wafer and generates a plurality of line images; and at least one processor configured to detect defects on the surface of the semiconductor wafer according to a set of predefined criteria. ### Claim 9 (depends on 8) The system of claim 8, wherein the transfer mechanism comprises a robotic transfer arm. ### Claim 10 (depends on 8) The system of claim 8, wherein the transfer mechanism is coupled to a wafer holder for holding the semiconductor wafer and exposing the surface of the semiconductor wafer. ### Claim 11 (depends on 8) The system of claim 8, wherein the at least one on-valve inspection detector comprises a line scan camera. ### Claim 12 (depends on 8) The system of claim 8, wherein the at least one on-valve inspection detector is configured to scan the surface of the semiconductor wafer one pixel line at a time. ### Claim 13 (depends on 8) The system of claim 8, wherein the at least one processor comprises a local computer configured to: receive the plurality of line images from the at least one on-valve inspection detector; and preprocess the plurality of line images to generate at least one surface image for the surface of the semiconductor wafer. ### Claim 14 (depends on 8) The system of claim 8, wherein the at least one processor further comprises a remote computer configured to: receive the at least one surface image from the local computer; analyze the at least one surface image; and compare the at least one surface image to the set of predefined criteria to detect defects on the surface of the semiconductor wafer. ### Claim 15 A wafer-level inspection system comprising: a processing chamber for performing a semiconductor manufacturing process; a vacuum valve for providing access through a transfer port of the processing chamber; a transfer mechanism configured to automatically transport a semiconductor wafer through the transfer port of the processing chamber; at least one on-valve inspection detector arranged on the vacuum valve to scan a surface of the semiconductor wafer; and at least one processor configured to detect defects on the surface of the semiconductor wafer according to a set of predefined criteria. ### Claim 16 (depends on 15) The system of claim 15, wherein the at least one on-valve inspection detector comprises a line scan camera. ### Claim 17 (depends on 15) The system of claim 15, wherein the at least one on-valve inspection detector is configured to scan the surface of the semiconductor wafer one pixel line at a time. ### Claim 18 (depends on 15) The system of claim 15, wherein the transfer mechanism is coupled to a wafer holder for holding the semiconductor wafer and exposing the surface of the semiconductor wafer. ### Claim 19 (depends on 15) The system of claim 15, wherein the at least one processor comprises a local computer configured to: receive a plurality of line images from the at least one on-valve inspection detector; and preprocess the plurality of line images to generate at least one surface image. ### Claim 20 (depends on 15) The system of claim 15, wherein the at least one processor further comprises a remote computer configured to: receive the at least one surface image from the local computer; analyze the at least one surface image; and compare the at least one surface image to the set of predefined criteria to detect defects on the surface of the semiconductor wafer.