# US 2019/0318933 A1 · Semiconductor device and method for fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0318933 A1
- Document ID: US20190318933A1
- Status: Published application
- Kind: A1
- Application number: 15/986,797
- Filed: 2018-05-22
- Published: 2019-10-17
- Earliest claimed: 2018-04-17
- Assignees: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Tzu-Hao Liu; Yi-Wei Chen; Tsun-Min Cheng; Kai-Jiun Chang; Chia-Chen Wu; Yi-An Huang; Po-Chih Wu; Pin-Hong Chen; Chun-Chieh Chiu; Tzu-Chieh Chen; Chih-Chien Liu; Chih-Chieh Tsai; Ji-Min Lin
- Web page: https://patentgrep.com/patent/US20190318933A1

## CPC

- H10D 64/01312: {the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 12/01: {Manufacture or treatment}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

## Claims

### Claim 1

A method for fabricating semiconductor device, comprising:
forming a titanium nitride (TiN) layer on a silicon layer;
performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer;
forming a conductive layer on the TiSiN layer; and
patterning the conductive layer, the TiSiN layer, and the silicon layer to form a gate structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the silicon layer comprises amorphous silicon.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a titanium (Ti) layer on the silicon layer; and
performing a second treatment process by reacting the Ti layer with ammonia (NH3) to form the TiN layer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming a metal silicide between the Ti layer and the silicon layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein a thickness of the metal silicide is less than a thickness of the TiN layer.

### Claim 6 (depends on 4)

The method of claim 4, wherein a thickness of the metal silicide is less than a thickness of the TiSiN layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the gate structure comprises a gate insulating layer on the substrate.

### Claim 8

A method for fabricating semiconductor device, comprising:
forming a titanium silicon nitride (TiSiN) layer on a silicon layer;
performing a first treatment process by reacting the TiSiN layer with ammonia (NH3) to form a nitrogen-rich layer;
forming a conductive layer on the nitrogen-rich layer; and
patterning the conductive layer, the nitrogen-rich layer, and the silicon layer to form a gate structure.

### Claim 9 (depends on 8)

The method of claim 8, wherein the silicon layer comprises amorphous silicon.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
forming a titanium (Ti) layer on the silicon layer;
performing a second treatment process by reacting the Ti layer with ammonia (NH3) to form a titanium nitride (TiN) layer; and
performing a third treatment process by reacting the TiN layer with dichlorosilane (DCS) to form the TiSiN layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming a metal silicide between the Ti layer and the silicon layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein a thickness of the metal silicide is less than a thickness of the TiN layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein a thickness of the metal silicide is less than a thickness of the TiSiN layer.

### Claim 14 (depends on 8)

The method of claim 8, wherein the gate structure comprises a gate insulating layer on the substrate.

### Claim 15

A semiconductor device, comprising:
a gate structure on a substrate, wherein the gate structure comprises:
a silicon layer on the substrate;
a titanium nitride (TiN) layer on the silicon layer;
a titanium silicon nitride (TiSiN) layer on the TiN layer; and
a conductive layer on the TiSiN layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a titanium (Ti) layer between the TiN layer and the silicon layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a metal silicide between the Ti layer and the silicon layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a thickness of the metal silicide is less than a thickness of the TiN layer.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein a thickness of the metal silicide is less than a thickness of the TiSiN layer.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, further comprising a nitrogen-rich layer between the TiSiN layer and the conductive layer.