# US 2019/0318928 A1 · Spacer image transfer with double mandrel

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- Number: US 2019/0318928 A1
- Document ID: US20190318928A1
- Status: Published application
- Kind: A1
- Application number: 15/951,266
- Filed: 2018-04-12
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Yann Mignot; Yongan Xu
- Web page: https://patentgrep.com/patent/US20190318928A1

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10P 50/242: {of Group IV materials}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 50/287: {by chemical means}
- H10P 76/2043: {using an anti-reflective coating}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for providing an etch mask for microelectronic processing that includes forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer. If a following step, the material stack may be patterned and etched to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer. A sidewall spacer is formed on sidewalls of the double mandrel structures.

## Claims

### Claim 1

A patterning method for microelectronic devices comprising:
forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer;
patterning the material stack to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer; and
forming a sidewall spacer on sidewalls of the double mandrel structures.

### Claim 2 (depends on 1)

The method of claim 1, wherein the base mandrel layer comprises a Ti containing material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the cap mandrel layer comprises an amorphous silicon containing material.

### Claim 4 (depends on 1)

The method of claim 1, wherein said forming the sidewall spacer comprises:
depositing a spacer material layer using a conformal deposition process; and
etching the spacer material layer with an anisotropic etch process to remove horizontally orientated portions of the spacer material layer, wherein vertically orientated portions of the spacer material layer remain to provide the sidewall spacer.

### Claim 5 (depends on 1)

The method of claim 1 further comprising etching the surface to be etched in a non-mandrel portion of a mask provided by the double mandrel structures and the sidewall spacer.

### Claim 6 (depends on 5)

The method of claim 5, further comprising etching the surface to be etched in a mandrel portion of a mask provided by the sidewall spacers following removing the cap mandrel layer and the base mandrel layer of the double mandrel structures.

### Claim 7 (depends on 5)

The method of claim 5, wherein the etching using the non-mandrel portion of the mask is conducted before the etching using the mandrel portion of the mask.

### Claim 8 (depends on 7)

The method of claim 7, wherein the etching using the non-mandrel portion of the mask is conducted after the etching using the mandrel portion of the mask.

### Claim 9 (depends on 1)

The method of claim 1, wherein the sidewall spacer present on sidewalls of the double mandrel structure is a first sidewall spacer, wherein the method further comprises:
removing the cap mandrel layer selectively to the base mandrel layer;
forming second sidewall spacers on inner and outer sidewalls of the first sidewall spacer;
removing the first sidewall spacer; and
etching the surface to be etched using a mask provided by the second sidewall spacers and the base dielectric layer of the double mandrel structures.

### Claim 10

A patterning method for microelectronic devices comprising:
forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop dielectric layers to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer;
patterning the material stack to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer;
forming a sidewall spacer on sidewalls of the double mandrel structures;
etching trenches in the dielectric layers using the double mandrel structures and sidewall spacers; and
filling the trenches with an electrically conductive material to provide metal lines.

### Claim 11 (depends on 10)

The method of claim 10, wherein said forming the sidewall spacer comprises:
depositing a spacer material layer using a conformal deposition process; and
etching the spacer material layer with an anisotropic etch process to remove horizontally orientated portions of the spacer material layer, wherein vertically orientated portions of the spacer material layer remain to provide the sidewall spacer.

### Claim 12 (depends on 10)

The method of claim 10, wherein said trenches are etched in the dielectric layers using a non-mandrel portion of the mask provided by the double mandrel structures and the sidewall spacer.

### Claim 13 (depends on 10)

The method of claim 10, wherein said trenches are etched in the dielectric layers using a mandrel portion of a mask provided by the sidewall spacers following removing the cap mandrel layer and the base mandrel layer of the double mandrel structures.

### Claim 14 (depends on 13)

The method of claim 13, wherein the etching using the non-mandrel portion of the mask is conducted before the etching using the mandrel portion of the mask, or the etching using the non-mandrel portion of the mask is conducted after the etching using the mandrel portion of the mask.

### Claim 15 (depends on 10)

The method of claim 10, wherein the sidewall spacer present on sidewalls of the double mandrel structure is a first sidewall spacer, wherein the method further comprises:
removing the cap mandrel layer selectively to the base mandrel layer;
forming second sidewall spacers on inner and outer sidewalls of the first sidewall spacer;
removing the first sidewall spacer; and
etching the dielectric layers using a mask provided by the second sidewall spacers and the base dielectric layer of the double mandrel structures.

### Claim 16

A patterning method for microelectronic devices comprising:
forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop semiconductor layers to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer;
patterning the material stack to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer;
forming a sidewall spacer on sidewalls of the double mandrel structures; and
etching fins in the semiconductors layers using the double mandrel structures and sidewall spacers.

### Claim 17 (depends on 16)

The method of claim 16, wherein said fins are etched in the semiconductor layers using a non-mandrel portion of the mask provided by the double mandrel structures and the sidewall spacer.

### Claim 18 (depends on 16)

The method of claim 16, wherein said fins are etched in the semiconductor layers using a mandrel portion of a mask provided by the sidewall spacers following removing the cap mandrel layer and the base mandrel layer of the double mandrel structures.

### Claim 19 (depends on 16)

The method of claim 16, wherein the etching using the non-mandrel portion of the mask is conducted before the etching using the mandrel portion of the mask, or the etching using the non-mandrel portion of the mask is conducted after the etching using the mandrel portion of the mask.

### Claim 20 (depends on 16)

The method of claim 16, wherein the sidewall spacer present on sidewalls of the double mandrel structure is a first sidewall spacer, wherein the method further comprises:
removing the cap mandrel layer selectively to the base mandrel layer;
forming second sidewall spacers on inner and outer sidewalls of the first sidewall spacer;
removing the first sidewall spacer; and
etching the semiconductor layers using a mask provided by the second sidewall spacers and the base dielectric layer of the double mandrel structures.