# US 2019/0318924 A1 · Semiconductor device

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- Number: US 2019/0318924 A1
- Document ID: US20190318924A1
- Status: Published application
- Kind: A1
- Application number: 16/348,290
- Filed: 2017-11-21
- Published: 2019-10-17
- Earliest claimed: 2016-12-02
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei YAMAZAKI
- Web page: https://patentgrep.com/patent/US20190318924A1

## CPC

- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- G02F 1/136277: {formed on a semiconductor substrate, e.g. of silicon}
- H05B 33/14: characterised by the chemical or physical composition or the arrangement of the electroluminescent material {, or by the simultaneous addition of the electroluminescent material in or onto the light source}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/3226: {Oxides}
- H10P 14/3234: {being oxide semiconducting materials (Group IIB-VIA semiconductors H10P14/3224)}
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6522: {introduced into a nitride material, e.g. changing SiN to SiON}
- H10P 14/6532: {by exposure to a plasma}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/6938: {the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10K 59/10: OLED displays
- H10K 59/40: OLEDs integrated with touch screens
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.

## Claims

### Claim 1

A semiconductor device containing a metal oxide, the semiconductor device comprising:
a gate electrode;
a first insulating film over the gate electrode;
the metal oxide over the first insulating film;
a pair of electrodes over the metal oxide; and
a second insulating film over the metal oxide,
wherein the metal oxide includes a source region, a drain region, a first region, a second region, and a third region,
wherein the source region is in contact with one of the pair of electrodes,
wherein the drain region is in contact with the other of the pair of electrodes,
wherein the first region, the second region, and the third region are each sandwiched between the source region and the drain region along a channel length direction,
wherein the second region is sandwiched between the first region and the third region along a channel width direction,
wherein the first region and the third region each include an end portion of the metal oxide, and
wherein the length of the second region along the channel length direction is less than the length of the first region or the length of the third region along the channel length direction.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the length of the second region along the channel length direction is greater than 0 μm and less than 4 μm, and
wherein the length of the first region or the length of the third region along the channel length direction is greater than three times the length of the second region along the channel length direction and less than the length of the metal oxide along the channel length direction.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the shortest path from the source region to the drain region is included in the second region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the metal oxide contains a first metal oxide and a second metal oxide in contact with a top surface of the first metal oxide,
wherein the first metal oxide and the second metal oxide each contain In, an element M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and Zn, and
wherein the first metal oxide includes a region having lower crystallinity than the second metal oxide.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein the first metal oxide and the second metal oxide each include a region where an In content is greater than or equal to 40% and less than or equal to 50% of the total number of In, M, and Zn atoms, and a region where an M content is greater than or equal to 5% and less than or equal to 30% of the total number of In, M and Zn atoms.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4,
wherein in each of the first metal oxide and the second metal oxide, the atomic ratio of M is greater than or equal to 1.5 and less than or equal to 2.5, and the atomic ratio of Zn is greater than or equal to 2 and less than or equal to 4 in the case where the atomic ratio of In is 4.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4,
wherein in each of the first metal oxide and the second metal oxide, the atomic ratio of M is greater than or equal to 0.5 and less than or equal to 1.5, and the atomic ratio of Zn is greater than or equal to 5 and less than or equal to 7 in the case where the atomic ratio of In is 5.

### Claim 8 (depends on 4)

The semiconductor device according to claim 4,
wherein a peak at around 2θ=31° is not observed in the first metal oxide and a peak at around 2θ=31° is observed in the second metal oxide in the case where the metal oxide is measured by XRD analysis.