# US 2019/0318800 A1 · Dram and method of designing the same

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- Number: US 2019/0318800 A1
- Document ID: US20190318800A1
- Status: Published application
- Kind: A1
- Application number: 15/955,076
- Filed: 2018-04-17
- Published: 2019-10-17
- Earliest claimed: 2018-04-17
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: TING-SHUO HSU; CHIH-WEI SHEN
- Web page: https://patentgrep.com/patent/US20190318800A1

## CPC

- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G11C 29/1201: {comprising I/O circuitry}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.

## Claims

### Claim 1

A dynamic random access memory (DRAM), comprising:
a first node configured to conduct a first internal signal generated by internal devices of the DRAM;
a second node configured to conduct a second internal signal generated by other internal devices of the DRAM; and
a pad configured to receive one of the first internal signal and the second internal signal.

### Claim 2 (depends on 1)

The DRAM of claim 1, comprising:
a first switch coupled between the first node and the pad; and
a second switch coupled between the second node and the pad,
wherein either the first switch couples the first node to the pad, or the second switch couples the second node to the pad.

### Claim 3 (depends on 2)

The DRAM of claim 2, wherein the first switch has a same circuit structure as the second switch.

### Claim 4 (depends on 3)

The DRAM of claim 3, wherein the first switch has same component parameters as the second switch.

### Claim 5 (depends on 1)

The DRAM of claim 1, wherein the DRAM is free of a micro pad.

### Claim 6 (depends on 1)

The DRAM of claim 1, wherein the second internal signal at the second node would otherwise be eligible to being tested by a probe only if a passivation layer of the DRAM was destroyed.

### Claim 7 (depends on 1)

The DRAM of claim 1, further comprising:
a third node configured to conduct a third internal signal generated by another internal device of the DRAM, wherein the third node is not connected to the pad.

### Claim 8 (depends on 1)

The DRAM of claim 1, further comprising:
a switch configured to connect either the first device or the second to the pad.

### Claim 9 (depends on 8)

The DRAM of claim 8, further comprising:
a third node configured to conduct a third internal signal generated by another internal device of the DRAM.

### Claim 10

A method of designing a dynamic random access memory (DRAM), the method comprising:
providing a first node configured for conducting a first internal signal;
providing a second node configured for conducting a second internal signal; and
providing a pad configured for receiving one of the first internal signal and the second internal signal.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
providing a first switch coupled between the first node and the pad; and
providing a second switch coupled between the second node and the pad,
wherein either the first switch couples the first node to the pad, or the second switch couples the second node to the pad.

### Claim 12 (depends on 11)

The method of claim 11, wherein the method does not include providing a micro pad.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
providing a third node configured for conducting a third internal signal generated by another internal device of the DRAM, wherein the third node is not connected to the pad.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
providing a switch configured for connecting either the first device or the second device to the pad.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
providing a third node configured for conducting a third internal signal generated by another internal device of the DRAM.

### Claim 16

A method of testing a dynamic random access memory (DRAM), the method comprising:
connecting one of a first node and a second node to a pad, wherein the first node is configured to conduct a first internal signal generated by internal devices of the DRAM, and wherein the second node is configured to conduct a second internal signal generated by other internal devices of the DRAM; and
testing the one of the first internal signal and the second internal signal by contacting the pad with a probe.

### Claim 17 (depends on 16)

The method of claim 16, wherein the operation of connecting one of a first node and a second node to a pad is performed by conducting one of a first switch and a second switch and not conducting the other one of the first switch and the second switch.

### Claim 18 (depends on 16)

The method of claim 16, wherein the operation of connecting one of a first node and a second node to a pad is performed by changing a conducted state of a switch, wherein one end of the switch is connected to the pad, and the other end of the switch is connected to the one of the first node and the second node.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
connecting the other one of the first node and the second node to the pad after connecting the one of the first node and the second node to the pad.