# US 2019/0318795 A1 · Semiconductor device

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- Number: US 2019/0318795 A1
- Document ID: US20190318795A1
- Status: Published application
- Kind: A1
- Application number: 16/501,539
- Filed: 2019-04-26
- Published: 2019-10-17
- Earliest claimed: 2012-02-29
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Atsushi Umezaki
- Web page: https://patentgrep.com/patent/US20190318795A1

## CPC

- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3674: {Details of drivers for scan electrodes}
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/3677: {suitable for active matrices only}
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- H10K 59/12: Active-matrix OLED [AMOLED] displays
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

## Claims

### Claim 1

(canceled)

### Claim 2

A semiconductor device comprising:
a gate driver; and
a pixel;
wherein the gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,
wherein a gate of the third transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the second power supply line,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a gate of the fourth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor,
wherein a gate of the seventh transistor is electrically connected to the second wiring,
wherein a first clock signal is input to the second wiring,
wherein a second clock signal is input to the third wiring,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the sixth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the seventh transistor,
wherein the ratio of the channel width to the channel length of the second transistor is larger than the ratio of the channel width to the channel length of the fourth transistor,
wherein the pixel comprises an eighth transistor, a ninth transistor and a light emitting element,
wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the light emitting element, and
wherein a gate of one of the eighth transistor and the ninth transistor is electrically connected to the first wiring.

### Claim 3 (depends on 2)

A semiconductor device according to claim 2,
wherein the pixel is configured to correct a video signal in accordance with a threshold voltage of the other of the eighth transistor and the ninth transistor, and
wherein the corrected video signal is supplied to a gate of the other of the eighth transistor and the ninth transistor.

### Claim 4

A semiconductor device comprising:
a gate driver comprising:
a first transistor,
a second transistor,
a third transistor,
a fourth transistor,
a fifth transistor,
a sixth transistor,
a seventh transistor,
an eighth transistor, and
a ninth transistor, and
a pixel portion,
wherein the gate driver is electrically connected to the pixel portion via a first wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is electrically connected to a fourth wiring,
wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the third transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the one of a source and a drain of the ninth transistor,
wherein a gate of the ninth transistor is electrically connected to the fourth wiring,
wherein the second wiring is a first power supply line,
wherein the third wiring is a second power supply line,
wherein the fourth wiring is a first clock signal line, and
wherein the fifth wiring is a second clock signal line.

### Claim 5 (depends on 4)

A semiconductor device according to claim 4, further comprising a pixel,
wherein the pixel comprises a tenth transistor, an eleventh transistor and a light emitting element,
wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the eleventh transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to the light emitting element, and
wherein a gate of one of the tenth transistor and the eleventh transistor is electrically connected to the first wiring.

### Claim 6 (depends on 5)

A semiconductor device according to claim 5,
wherein the pixel is configured to correct a video signal in accordance with a threshold voltage of the other of the tenth transistor and the eleventh transistor, and
wherein the corrected video signal is supplied to a gate of the other of the tenth transistor and the eleventh transistor.

### Claim 7 (depends on 4)

A semiconductor device according to claim 4,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor, and
wherein the ratio of a channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the eighth transistor.

### Claim 8

A semiconductor device comprising:
a gate driver comprising:
a first transistor,
a second transistor,
a third transistor,
a fourth transistor,
a fifth transistor,
a sixth transistor,
a seventh transistor,
an eighth transistor, and
a ninth transistor, and
a pixel portion,
wherein the gate driver is electrically connected to the pixel portion via a first wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is electrically connected to a fourth wiring,
wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to a gate of the seventh transistor,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the third wiring,
wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a fifth wiring,
wherein the gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the one of a source and a drain of the ninth transistor,
wherein a gate of the ninth transistor is electrically connected to the fourth wiring,
wherein the second wiring is a first power supply line,
wherein the third wiring is a second power supply line,
wherein the fourth wiring is a first clock signal line, and
wherein the fifth wiring is a second clock signal line.

### Claim 9 (depends on 8)

A semiconductor device according to claim 8, further comprising a pixel,
wherein the pixel comprises a tenth transistor, an eleventh transistor and a light emitting element,
wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the eleventh transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to the light emitting element, and
wherein a gate of one of the tenth transistor and the eleventh transistor is electrically connected to the first wiring.

### Claim 10 (depends on 9)

A semiconductor device according to claim 9,
wherein the pixel is configured to correct a video signal in accordance with a threshold voltage of the other of the tenth transistor and the eleventh transistor, and
wherein the corrected video signal is supplied to a gate of the other of the tenth transistor and the eleventh transistor.

### Claim 11 (depends on 8)

A semiconductor device according to claim 8,
wherein a gate of the fifth transistor is electrically connected to the one of the source and the drain of the eighth transistor, and
wherein a gate of the sixth transistor is electrically connected to the one of the source and the drain of the third transistor.

### Claim 12 (depends on 8)

A semiconductor device according to claim 8,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor, and
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the eighth transistor.