# US 2019/0318794 A1 · Liquid Crystal Display Device and Electronic Device Including the Same

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- Number: US 2019/0318794 A1
- Document ID: US20190318794A1
- Status: Published application
- Kind: A1
- Application number: 16/447,357
- Filed: 2019-06-20
- Published: 2019-10-17
- Earliest claimed: 2009-01-16
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Atsushi Umezaki
- Web page: https://patentgrep.com/patent/US20190318794A1

## CPC

- G09G 3/3674: {Details of drivers for scan electrodes}
- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10W 20/43: Layouts of interconnections
- G02F 1/13606: {having means for reducing parasitic capacitance}
- G02F 2201/124: interdigital
- G09G 3/3688: {suitable for active matrices only}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

## Claims

### Claim 1

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor, one of a source electrode and a drain electrode of the eleventh transistor, one of a source electrode and a drain electrode of the twelfth transistor, and one of a source electrode and a drain electrode of the fourteenth transistor,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, one of a source electrode and a drain electrode of the third transistor, one of a source electrode and a drain electrode of the fifth transistor, a gate electrode of the seventh transistor, a gate electrode of the ninth transistor, one of a source electrode and a drain electrode of the tenth transistor, and one of a source electrode and a drain electrode of the thirteenth transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a gate electrode of the second transistor, and the other of the source electrode and the drain electrode of the third transistor,
wherein a gate electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor, one of a source electrode and a drain electrode of the eighth transistor, a gate electrode of the eighth transistor, and a gate electrode of the twelfth transistor,
wherein a gate electrode of the fourth transistor is electrically connected to a gate electrode of the fifth transistor, the other of the source electrode and the drain electrode of the sixth transistor, and one of a source electrode and a drain electrode of the seventh transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the other of the source electrode and the drain electrode of the eighth transistor, and one of a source electrode and a drain electrode of the ninth transistor,
wherein a gate electrode of the tenth transistor is electrically connected to a gate electrode of the eleventh transistor,
wherein a gate electrode of the thirteenth transistor is electrically connected to a gate electrode of the fourteenth transistor.

### Claim 2

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor, one of a source electrode and a drain electrode of the eleventh transistor, one of a source electrode and a drain electrode of the twelfth transistor, one of a source electrode and a drain electrode of the fourteenth transistor, and a first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first clock signal line,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, one of a source electrode and a drain electrode of the third transistor, one of a source electrode and a drain electrode of the fifth transistor, a gate electrode of the seventh transistor, a gate electrode of the ninth transistor, one of a source electrode and a drain electrode of the tenth transistor, and one of a source electrode and a drain electrode of the thirteenth transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a gate electrode of the second transistor, the other of the source electrode and the drain electrode of the third transistor, and a second gate line,
wherein a gate electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor, one of a source electrode and a drain electrode of the eighth transistor, a gate electrode of the eighth transistor, a gate electrode of the twelfth transistor, and a second clock signal line,
wherein a gate electrode of the fourth transistor is electrically connected to a gate electrode of the fifth transistor, the other of the source electrode and the drain electrode of the sixth transistor, and one of a source electrode and a drain electrode of the seventh transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the other of the source electrode and the drain electrode of the eighth transistor, and one of a source electrode and a drain electrode of the ninth transistor,
wherein a gate electrode of the tenth transistor is electrically connected to a gate electrode of the eleventh transistor, and a third gate line,
wherein a gate electrode of the thirteenth transistor is electrically connected to a gate electrode of the fourteenth transistor,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the other of the source electrode and the drain electrode of the fifth transistor, the other of the source electrode and the drain electrode of the seventh transistor, the other of the source electrode and the drain electrode of the ninth transistor, the other of the source electrode and the drain electrode of the tenth transistor, the other of the source electrode and the drain electrode of the eleventh transistor, the other of the source electrode and the drain electrode of the twelfth transistor, the other of the source electrode and the drain electrode of the thirteenth transistor, the other of the source electrode and the drain electrode of the fourteenth transistor, and a power supply line.

### Claim 3

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor, one of a source electrode and a drain electrode of the eleventh transistor, one of a source electrode and a drain electrode of the twelfth transistor, one of a source electrode and a drain electrode of the fourteenth transistor, and a first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first clock signal line,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, one of a source electrode and a drain electrode of the third transistor, one of a source electrode and a drain electrode of the fifth transistor, a gate electrode of the seventh transistor, a gate electrode of the ninth transistor, one of a source electrode and a drain electrode of the tenth transistor, and one of a source electrode and a drain electrode of the thirteenth transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a gate electrode of the second transistor, the other of the source electrode and the drain electrode of the third transistor, and a second gate line,
wherein a gate electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor, one of a source electrode and a drain electrode of the eighth transistor, a gate electrode of the eighth transistor, a gate electrode of the twelfth transistor, and a second clock signal line,
wherein a gate electrode of the fourth transistor is electrically connected to a gate electrode of the fifth transistor, the other of the source electrode and the drain electrode of the sixth transistor, and one of a source electrode and a drain electrode of the seventh transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the other of the source electrode and the drain electrode of the eighth transistor, and one of a source electrode and a drain electrode of the ninth transistor,
wherein a gate electrode of the tenth transistor is electrically connected to a gate electrode of the eleventh transistor, and a third gate line,
wherein a gate electrode of the thirteenth transistor is electrically connected to a gate electrode of the fourteenth transistor, and a signal line to which a reset signal is input,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the other of the source electrode and the drain electrode of the fifth transistor, the other of the source electrode and the drain electrode of the seventh transistor, the other of the source electrode and the drain electrode of the ninth transistor, the other of the source electrode and the drain electrode of the tenth transistor, the other of the source electrode and the drain electrode of the eleventh transistor, the other of the source electrode and the drain electrode of the twelfth transistor, the other of the source electrode and the drain electrode of the thirteenth transistor, the other of the source electrode and the drain electrode of the fourteenth transistor, and a power supply line.

### Claim 4

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor, one of a source electrode and a drain electrode of the eleventh transistor, one of a source electrode and a drain electrode of the twelfth transistor, one of a source electrode and a drain electrode of the fourteenth transistor, and a first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first clock signal line,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, one of a source electrode and a drain electrode of the third transistor, one of a source electrode and a drain electrode of the fifth transistor, a gate electrode of the seventh transistor, a gate electrode of the ninth transistor, one of a source electrode and a drain electrode of the tenth transistor, and one of a source electrode and a drain electrode of the thirteenth transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a gate electrode of the second transistor, the other of the source electrode and the drain electrode of the third transistor, and a second gate line,
wherein a gate electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor, one of a source electrode and a drain electrode of the eighth transistor, a gate electrode of the eighth transistor, a gate electrode of the twelfth transistor, and a second clock signal line,
wherein a gate electrode of the fourth transistor is electrically connected to a gate electrode of the fifth transistor, the other of the source electrode and the drain electrode of the sixth transistor, and one of a source electrode and a drain electrode of the seventh transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the other of the source electrode and the drain electrode of the eighth transistor, and one of a source electrode and a drain electrode of the ninth transistor,
wherein a gate electrode of the tenth transistor is electrically connected to a gate electrode of the eleventh transistor, and a third gate line,
wherein a gate electrode of the thirteenth transistor is electrically connected to a gate electrode of the fourteenth transistor,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the other of the source electrode and the drain electrode of the fifth transistor, the other of the source electrode and the drain electrode of the seventh transistor, the other of the source electrode and the drain electrode of the ninth transistor, the other of the source electrode and the drain electrode of the tenth transistor, the other of the source electrode and the drain electrode of the eleventh transistor, the other of the source electrode and the drain electrode of the twelfth transistor, the other of the source electrode and the drain electrode of the thirteenth transistor, the other of the source electrode and the drain electrode of the fourteenth transistor, and a power supply line,
wherein, in the first transistor, an area where the one of the source electrode and the drain electrode overlaps with the gate electrode is larger than an area where the other of the source electrode and the drain electrode overlaps with the gate electrode,
wherein, in the second transistor, an area where the one of the source electrode and the drain electrode overlaps with the gate electrode is smaller than an area where the other of the source electrode and the drain electrode overlaps with the gate electrode,
wherein, in the third transistor, an area where the one of the source electrode and the drain electrode overlaps with the gate electrode is smaller than an area where the other of the source electrode and the drain electrode overlaps with the gate electrode.