# US 2019/0318791 A1 · Memory management method, memory storage device and memory control circuit unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318791 A1 - Document ID: US20190318791A1 - Status: Published application - Kind: A1 - Application number: 16/003,114 - Filed: 2018-06-08 - Published: 2019-10-17 - Earliest claimed: 2018-04-16 - Assignees: Phison Electronics Corp. - Applicants: Phison Electronics Corp. - Inventors: Wei Lin; An-Cheng Liu; Szu-Wei Chen; Yu-Siang Yang - Web page: https://patentgrep.com/patent/US20190318791A1 ## CPC - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level. ## Claims ### Claim 1 A memory management method for a memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory management method comprises: programming first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level. ### Claim 2 (depends on 1) The memory management method according to claim 1, further comprising: randomizing original data to generate the first data. ### Claim 3 (depends on 1) The memory management method according to claim 1, wherein the default count information corresponding to the first read voltage level reflects a default memory cell count. ### Claim 4 (depends on 1) The memory management method according to claim 1, wherein a value of the default count information corresponding to the first read voltage level is positively correlated with a total number of the plurality of first memory cells, and the value of the default count information corresponding to the first read voltage level is negatively correlated with a total number of the plurality of states. ### Claim 5 (depends on 1) The memory management method according to claim 1, further comprising: obtaining the default count information corresponding to the first read voltage level according to Equation (1) below: C=i×(N/M) (1), wherein in Equation (1), the parameter C represents the default count information corresponding to the first read voltage level, the parameter i represents an index value corresponding to the first read voltage level, the parameter N represents a total number of the plurality of first memory cells, and the parameter M represents a total number of the plurality of states. ### Claim 6 (depends on 1) The memory management method according to claim 1, wherein the first count information corresponding to the first read voltage level reflects a number of at least one memory cell each having a voltage level that is not greater than the first read voltage level among the programmed first memory cells. ### Claim 7 (depends on 1) The memory management method according to claim 1, wherein the step of adjusting the first read voltage level according to the first count information and the default count information corresponding to the first read voltage level comprises: determining a first adjustment value according to the first count information and the default count information; and adjusting the first read voltage level according to the first adjustment value. ### Claim 8 (depends on 7) The memory management method according to claim 7, wherein the step of adjusting the first read voltage level according to the first adjustment value comprises: sending a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first adjustment value; determining a second adjustment value according to a read result corresponding to the second single-stage read command sequence; and adjusting the first read voltage level according to the first adjustment value and the second adjustment value. ### Claim 9 A memory storage device comprising: a connection interface unit configured to couple to a host system; a rewritable non-volatile memory module comprising a plurality of memory cells; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to send a write command sequence which indicates to program first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value, wherein the memory control circuit unit is further configured to send a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level, wherein the memory control circuit unit is further configured to obtain first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence, and wherein the memory control circuit unit is further configured to adjust the first read voltage level according to the first count information and default count information corresponding to the first read voltage level. ### Claim 10 (depends on 9) The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to randomize original data to generate the first data. ### Claim 11 (depends on 9) The memory storage device according to claim 9, wherein the default count information corresponding to the first read voltage level reflects a default memory cell count. ### Claim 12 (depends on 9) The memory storage device according to claim 9, wherein a value of the default count information corresponding to the first read voltage level is positively correlated with a total number of the plurality of first memory cells, and the value of the default count information corresponding to the first read voltage level is negatively correlated with a total number of the plurality of states. ### Claim 13 (depends on 9) The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to obtain the default count information corresponding to the first read voltage level according to Equation (1) below: C=i×(N/M) (1), wherein in Equation (1), the parameter C represents the default count information corresponding to the first read voltage level, the parameter i represents an index value corresponding to the first read voltage level, the parameter N represents a total number of the plurality of first memory cells, and the parameter M represents a total number of the plurality of states. ### Claim 14 (depends on 9) The memory storage device according to claim 9, wherein the first count information corresponding to the first read voltage level reflects a number of at least one memory cell each having a voltage level that is not greater than the first read voltage level among the programmed first memory cells. ### Claim 15 (depends on 9) The memory storage device according to claim 9, wherein the operation of adjusting the first read voltage level according to the first count information and the default count information corresponding to the first read voltage level by the memory control circuit unit comprises: determining a first adjustment value according to the first count information and the default count information; and adjusting the first read voltage level according to the first adjustment value. ### Claim 16 (depends on 15) The memory storage device according to claim 15, wherein the operation of adjusting the first read voltage level according to the first adjustment value by the memory control circuit unit comprises: sending a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first adjustment value; determining a second adjustment value according to a read result corresponding to the second single-stage read command sequence; and adjusting the first read voltage level according to the first adjustment value and the second adjustment value. ### Claim 17 A memory control circuit unit configured to control a rewritable non-volatile memory module comprising a plurality of memory cells, the memory control circuit unit comprising: a host interface configured to couple to a host system; a memory interface configured to couple to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit is configured to send a write command sequence which indicates to program first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value, wherein the memory management circuit is further configured to send a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level, wherein the memory management circuit is further configured to obtain first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence, and wherein the memory management circuit is further configured to adjust the first read voltage level according to the first count information and default count information corresponding to the first read voltage level. ### Claim 18 (depends on 17) The memory control circuit unit according to claim 17, wherein the memory management circuit is further configured to randomize original data to generate the first data. ### Claim 19 (depends on 17) The memory control circuit unit according to claim 17, wherein the default count information corresponding to the first read voltage level reflects a default memory cell count. ### Claim 20 (depends on 17) The memory control circuit unit according to claim 17, wherein a value of the default count information corresponding to the first read voltage level is positively correlated with a total number of the plurality of first memory cells, and the value of the default count information corresponding to the first read voltage level is negatively correlated with a total number of the plurality of states. ### Claim 21 (depends on 17) The memory control circuit unit according to claim 17, wherein the memory management circuit is further configured to obtain the default count information corresponding to the first read voltage level according to Equation (1) below: C=i×(N/M) (1), wherein in Equation (1), the parameter C represents the default count information corresponding to the first read voltage level, the parameter i represents an index value corresponding to the first read voltage level, the parameter N represents a total number of the plurality of first memory cells, and the parameter M represents a total number of the plurality of states. ### Claim 22 (depends on 17) The memory control circuit unit according to claim 17, wherein the first count information corresponding to the first read voltage level reflects a number of at least one memory cell each having a voltage level that is not greater than the first read voltage level among the programmed first memory cells. ### Claim 23 (depends on 17) The memory control circuit unit according to claim 17, wherein the operation of adjusting the first read voltage level according to the first count information and the default count information corresponding to the first read voltage level by the memory management circuit comprises: determining a first adjustment value according to the first count information and the default count information; and adjusting the first read voltage level according to the first adjustment value. ### Claim 24 (depends on 23) The memory control circuit unit according to claim 23, wherein the operation of adjusting the first read voltage level according to the first count information and the default count information by the memory management circuit comprises: sending a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first adjustment value; determining a second adjustment value according to a read result corresponding to the second single-stage read command sequence; and adjusting the first read voltage level according to the first adjustment value and the second adjustment value. ### Claim 25 A memory management method for a memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory management method comprises: in a first read mode, sending a first single-stage read command sequence which indicates to read a plurality of first memory cells being programmed among the plurality of memory cells by using a first read voltage level, wherein response information of the first single-stage read command sequence comprises first count information for adjusting the first read voltage level; and in the first read mode, sending a first common read command sequence which indicates to read the plurality of first memory cells by using the adjusted first read voltage level, wherein response information of the first common read command sequence is used to generate read data requested by a host system. ### Claim 26 (depends on 25) The memory management method according to claim 25, further comprising: in a second read mode, sending at least one second common read command sequence which indicates to read the plurality of first memory cells by using a plurality of third read voltage levels, wherein response information of the at least one second common read command sequence is used to generate the read data requested by the host system, and a number of the plurality of third read voltage levels is greater than a number of the first read voltage level.