# US 2019/0318789 A1 · Charge pump drive circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318789 A1 - Document ID: US20190318789A1 - Status: Published application - Kind: A1 - Application number: 16/226,094 - Filed: 2018-12-19 - Published: 2019-10-17 - Earliest claimed: 2018-04-12 - Assignees: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Applicants: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Inventors: Yuan TANG; Zhifeng MAO; Yi XU; Hung-Yu CHANG; Jen-Tai HSU - Web page: https://patentgrep.com/patent/US20190318789A1 ## CPC - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 16/30: Power supply circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K 5/24: the characteristic being amplitude - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 2207/2227: Standby or low power modes - G11C: STATIC STORES (semiconductor memory devices H10B) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V. ## Claims ### Claim 1 A charge pump drive circuit for providing a charge pump with a switch signal, the charge pump configured to provide a memory with a read voltage and a read current, the charge pump drive circuit comprising a read drive circuit and a standby drive circuit, wherein: the read drive circuit is powered by a first power supply and provides the charge pump with a first switch signal when the memory is in a read active state; the standby drive circuit is powered by a second power supply and provides the charge pump with a second switch signal when the memory is in a read standby state; and the first power supply provides a voltage level ranging from 1.6 V to 3.8 V and the second power supply provides a voltage level of 1.5 V. ### Claim 2 (depends on 1) The charge pump drive circuit of claim 1, further comprising an OR gate having two inputs connected respectively to an output of the read drive circuit and an output of the standby drive circuit and an output connected to the charge pump. ### Claim 3 (depends on 2) The charge pump drive circuit of claim 2, wherein when the memory is in a writing, erasing or programming state, the read drive circuit provides the charge pump with the first switch signal. ### Claim 4 (depends on 3) The charge pump drive circuit of claim 3, further comprising a first signal selection circuit and a second signal selection circuit, wherein: the first signal selection circuit is provided with a first reference signal, a second reference signal and a selection signal; the second signal selection circuit is provided with a first feedback voltage, a second feedback voltage and the selection signal; the selection signal is dependent on the state of the memory; when the memory is in the read active state or the read standby state, the selection signal causes the first signal selection circuit to output the first reference signal and causes the second signal selection circuit to output the first feedback voltage; and when the memory is in the writing, erasing or programming state, the selection signal causes the first signal selection circuit to output the second reference signal and causes the second signal selection circuit to output the second feedback voltage. ### Claim 5 (depends on 4) The charge pump drive circuit of claim 4, further comprising a first resistor network and a second resistor network, wherein: each of the first resistor network and the second resistor network is connected between an output of the charge pump and a ground; and the first feedback voltage is coupled to the first resistor network and the second feedback voltage is coupled to the second resistor network. ### Claim 6 (depends on 4) The charge pump drive circuit of claim 4, wherein the read drive circuit comprises a first comparator and a first voltage controlled oscillator (VCO), the first comparator having a non-inverting input connected to an output of the first signal selection circuit, the first comparator having an inverting input connected to an output of the second signal selection circuit, the first comparator having an output connected to an input of the first VCO, the first VCO having an output serving as the output of the read drive circuit. ### Claim 7 (depends on 6) The charge pump drive circuit of claim 6, wherein the read drive circuit further comprises two first switches, wherein the first power supply respectively powers the first comparator and the first VCO via the two first switches, and wherein the first switches are opened or closed under control of a first switch signal. ### Claim 8 (depends on 4) The charge pump drive circuit of claim 4, wherein the standby drive circuit comprises a second comparator and a second VCO, the second comparator having a non-inverting input connected to an output of the first signal selection circuit, the second comparator having an inverting input connected to an output of the second signal selection circuit, the second comparator having an output connected to an input of the second VCO, the second VCO having an output serving as the output of the standby drive circuit. ### Claim 9 (depends on 8) The charge pump drive circuit of claim 8, wherein the standby drive circuit further comprises two second switches, wherein the second power supply respectively powers the second comparator and the second VCO via the two second switches, and wherein the second switches are opened or closed under control of a second switch signal. ### Claim 10 (depends on 8) The charge pump drive circuit of claim 8, further comprising an electrical level shifting circuit connected between the output of the second VCO and one of the inputs of the OR gate. ### Claim 11 A charge pump drive circuit for providing a charge pump with a switch signal, the charge pump configured to provide a memory with a read voltage and a read current, the charge pump drive circuit comprising a read drive circuit, a standby drive circuit and an OR gate, wherein: the read drive circuit is powered by a first power supply and provides a first switch signal for the charge pump when the memory is in a read active state; the standby drive circuit is powered by a second power supply and provides a second switch signal for the charge pump when the memory is in a read standby state; the OR gate has two inputs connected respectively to an output of the read drive circuit and an output of the standby drive circuit and an output connected to the charge pump; and the first power supply provides a voltage level ranging from 1.6 V to 3.8 V and the second power supply provides a constant voltage lower than the first power supply. ### Claim 12 (depends on 11) The charge pump drive circuit of claim 11, wherein when the memory is in a writing, erasing or programming state, the read drive circuit provides the first switch signal for the charge pump. ### Claim 13 (depends on 12) The charge pump drive circuit of claim 12, further comprising a first signal selection circuit and a second signal selection circuit, wherein: the first signal selection circuit is provided with a first reference signal, a second reference signal and a selection signal; the second signal selection circuit is provided with a first feedback voltage, a second feedback voltage and the selection signal; the selection signal is dependent on the state of the memory; when the memory is in the read active state or the read standby state, the selection signal causes the first signal selection circuit to output the first reference signal and causes the second signal selection circuit to output the first feedback voltage; and when the memory is in the writing, erasing or programming state, the selection signal causes the first signal selection circuit to output the second reference signal and causes the second signal selection circuit to output the second feedback voltage. ### Claim 14 (depends on 13) The charge pump drive circuit of claim 13, further comprising a first resistor network and a second resistor network, wherein: each of the first resistor network and the second resistor network is connected between an output of the charge pump and a ground; and the first feedback voltage is coupled to the first resistor network and the second feedback voltage is coupled to the second resistor network. ### Claim 15 (depends on 13) The charge pump drive circuit of claim 13, wherein the read drive circuit comprises a first comparator and a first voltage controlled oscillator (VCO), the first comparator having a non-inverting input connected to an output of the first signal selection circuit, the first comparator having an inverting input connected to an output of the second signal selection circuit, the first comparator having an output connected to an input of the first VCO, the first VCO having an output serving as the output of the read drive circuit. ### Claim 16 (depends on 15) The charge pump drive circuit of claim 15, wherein the read drive circuit further comprises two first switches, wherein the first power supply respectively powers the first comparator and the first VCO via the two first switches, and wherein the first switches are opened or closed under control of a first switch signal. ### Claim 17 (depends on 13) The charge pump drive circuit of claim 13, wherein the standby drive circuit comprises a second comparator and a second VCO, the second comparator having a non-inverting input connected to an output of the first signal selection circuit, the second comparator having an inverting input connected to an output of the second signal selection circuit, the second comparator having an output connected to an input of the second VCO, the second VCO having an output serving as the output of the standby drive circuit. ### Claim 18 (depends on 17) The charge pump drive circuit of claim 17, wherein the standby drive circuit further comprises two second switches, wherein the second power supply respectively powers the second comparator and the second VCO via the two second switches, and wherein the second switches are opened or closed under control of a second switch signal. ### Claim 19 (depends on 17) The charge pump drive circuit of claim 17, further comprising an electrical level shifting circuit connected between the output of the second VCO and one of the inputs of the OR gate.