# US 2019/0318787 A1 · Non-volatile memory device and initialization information reading method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318787 A1 - Document ID: US20190318787A1 - Status: Published application - Kind: A1 - Application number: 16/181,176 - Filed: 2018-11-05 - Published: 2019-10-17 - Earliest claimed: 2018-04-12 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: YOUN-YEOL LEE; WOOK-GHEE HAHN - Web page: https://patentgrep.com/patent/US20190318787A1 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/20: Initialising; Data preset; Chip identification - G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells - G11C 16/30: Power supply circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells. ## Claims ### Claim 1 A non-volatile memory device, comprising: a memory cell array configured to store initialization information for the non-volatile memory device in memory cells connected to a plurality of word lines; a control circuit configured to control application of a first read voltage to a selected word line and to control application of a second read voltage to unselected word lines in an initialization information read operation of reading the initialization information; and a voltage generator configured to decrease a source voltage to generate the second read voltage in response to a voltage control signal provided from the control circuit in the initialization information read operation. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, wherein the memory cells are single level cells storing one-bit data. ### Claim 3 (depends on 2) The non-volatile memory device of claim 2, wherein the first read voltage is set to have a voltage level for discriminating between erase states and program states of the single level cells. ### Claim 4 (depends on 3) The non-volatile memory device of claim 3, wherein the first read voltage is set as a ground voltage. ### Claim 5 (canceled) ### Claim 6 (depends on 1) The non-volatile memory device of claim 1, wherein the control circuit is configured to detect power-up to generate the voltage control signal. ### Claim 7 (depends on 1) The non-volatile memory device of claim 1, wherein the voltage generator is configured to allow the source voltage not to be pumped in response to the voltage control signal. ### Claim 8 (depends on 1) The non-volatile memory device of claim 1, wherein the voltage generator comprises: a voltage divider including a plurality of resistors serially connected between the source voltage and a ground voltage, the voltage divider being configured to generate division voltages at both ends of each of the plurality of resistors; and a selector configured to output one of the division voltages as the second read voltage in response to the voltage control signal. ### Claim at position 9 9-13. (canceled) ### Claim 14 (depends on 1) The non-volatile memory device of claim 1, further comprising a set register storing the initialization information read through the initialization information read operation. ### Claim 15 (depends on 1) The non-volatile memory device of claim 1, wherein the initialization information comprises protection information about inhibition or permission of program or erase operations performed on the memory cell array, trimming data for trimming an operating voltage level in a program, read, or erase operation mode of the non-volatile memory device, column repair information for repairing a failed bit line of the non-volatile memory device, or bad block information identifying bad memory cells of the non-volatile memory device. ### Claim at position 12 16-25. (canceled) ### Claim 26 A read method of a non-volatile memory device, the read method comprising: detecting power-up; in response to the detected power-up, reading initialization information for the non-volatile memory device stored in memory cells of the non-volatile memory device; and when reading the initialization information, generating a first read voltage which is to be provided to a selected word line of a plurality of word lines connected to the memory cells, and generating a second read voltage which is to be provided to unselected word lines of the plurality of word lines connected to the memory cells, wherein the second read voltage is generated by reducing a source voltage. ### Claim 27 (depends on 26) The read method of claim 26, further comprising allowing the source voltage not to be pumped in response to a voltage control signal associated with the power-up. ### Claim 28 (depends on 26) The read method of claim 26, wherein the generating of the second read voltage comprises dividing the source voltage, in response to a voltage control signal, to generate the second read voltage. ### Claim 29 (depends on 26) The read method of claim 26, wherein the memory cells are single level cells storing one-bit data. ### Claim at position 17 30-32. (canceled) ### Claim 33 (depends on 26) The read method of claim 26, further comprising setting the read initialization information in a set register. ### Claim 34 (depends on 26) The read method of claim 26, wherein the initialization information comprises protection information about inhibition or permission of program or erase operations on the non-volatile memory device, trimming data for trimming an operating voltage level in a program, read, or erase operation mode for the non-volatile memory device, column repair information for repairing a failed bit line of the non-volatile memory device, or bad block information identifying bad memory cells of the non-volatile memory device. ### Claim 35 A method, comprising: a non-volatile memory device detecting a power-up state for the memory device; and in response to detecting the power up state, the non-volatile memory device reading initialization information for the non-volatile memory device which is stored in first memory cells of a memory cell array of the non-volatile memory device and setting the initialization information for the non-volatile memory device in a set register of the non-volatile memory device, wherein reading the initialization information for the non-volatile memory device which is stored in first memory cells of the memory cell array of the non-volatile memory device comprises: applying to selected word lines connected to the first memory cells a first read voltage having a first read voltage level for discriminating between erase states and program states of the first memory cells; and while applying the first read voltage to the selected word lines, applying to unselected word lines which are not connected to the first memory cells a second read voltage having a second read voltage level which is less than voltage levels of the programs states of the first memory cells. ### Claim 36 (depends on 35) The method of claim 35, further comprising the non-volatile memory device: receiving a source voltage which is less than the voltage levels of the programs states of the first memory cells; and applying the source voltage to a low voltage generation circuit to generate the second read voltage which is less than voltage levels of the programs states of the first memory cells. ### Claim 37 (depends on 36) The method of claim 36, wherein the second read voltage level is between a ground voltage level and a level of the source voltage. ### Claim 38 (depends on 35) The method of claim 35, wherein the second read voltage level is a ground voltage level. ### Claim 39 (depends on 35) The method of claim 35, wherein the initialization information comprises protection information about inhibition or permission of program or erase operations on the non-volatile memory device, trimming data for trimming an operating voltage level in a program, read, or erase operation mode for the non-volatile memory device, column repair information for repairing a failed bit line of the non-volatile memory device, or bad block information identifying bad memory cells of the non-volatile memory device.