# US 2019/0318786 A1 · Storage device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318786 A1 - Document ID: US20190318786A1 - Status: Published application - Kind: A1 - Application number: 16/172,333 - Filed: 2018-10-26 - Published: 2019-10-17 - Earliest claimed: 2018-04-17 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Gi Pyo UM - Web page: https://patentgrep.com/patent/US20190318786A1 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G06F 3/064: {Management of blocks} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G11C 7/109: {Control signal input circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G11C 16/32: Timing circuits - G11C 2207/2227: Standby or low power modes - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including a plurality of memory blocks, and a memory controller configured to control the memory device to perform a background erase operation on at least one free block of the plurality of memory blocks based on information about a size of write data to be provided to the memory device. ## Claims ### Claim 1 A storage device comprising: a memory device including a plurality of memory blocks; and a memory controller configured to control the memory device to perform a background erase operation on at least one free block of the plurality of memory blocks based on information about a size of write data to be provided to the memory device. ### Claim 2 (depends on 1) The storage device according to claim 1, wherein, when a normal operation command is inputted from the memory controller while the background erase operation is performed, the memory device suspends the background erase operation in response to input of a confirm command of the normal operation command. ### Claim 3 (depends on 1) The storage device according to claim 1, wherein the memory controller comprises: a background erase operation controller configured to provide triggering information instructing the background erase operation to be performed based on the information about the size of the write data; and a command generator configured to generate a background erase operation command instructing the background erase operation to be performed on the at least one free block based on the triggering information. ### Claim 4 (depends on 1) The storage device according to claim 1, wherein the background erase operation controller generates write count information obtained by accumulating the information about the size of the write data, and determines whether the write count information exceeds a preset reference value. ### Claim 5 (depends on 4) The storage device according to claim 4, wherein the preset reference value is a value corresponding to a size of any one of the plurality of memory blocks. ### Claim 6 (depends on 4) The storage device according to claim 4, wherein the memory controller further comprises a write count information storage configured to store the write count information. ### Claim 7 (depends on 3) The storage device according to claim 3, wherein the memory controller further comprises a block management component configured to store a free block list which includes information about addresses of a plurality of free blocks included in the memory device. ### Claim 8 (depends on 7) The storage device according to claim 7, wherein, in response to the triggering information, the command generator generates the background erase operation command for a free block having a lowest erase operation count among the plurality of free blocks included in the free block list. ### Claim 9 (depends on 2) The storage device according to claim 2, wherein the normal operation command includes a first command, and a second command indicating that an address and data needed to perform the first command have been completely inputted. ### Claim 10 (depends on 9) The storage device according to claim 9, wherein the first command comprises a start command indicating a type of the normal operation command, and wherein the second command comprises the confirm command. ### Claim 11 (depends on 2) The storage device according to claim 2, wherein the normal operation command comprises a command corresponding to any one of a program operation, a read operation, and an erase operation. ### Claim 12 A method of operating a memory controller configured to control a memory device including a plurality of memory blocks, the method comprising: obtaining information about a size of write data to be provided to the memory device; and instructing the memory device to perform a background erase operation on at least one free block of the plurality of memory blocks based on the information about the size of the write data. ### Claim 13 (depends on 12) The method according to claim 12, wherein the instructing comprises: generating write count information obtained by accumulating the information of the size of the write data; and providing a background erase command instructing the background erase operation to be performed on the at least one free block depending on whether the write count information exceeds a preset reference value. ### Claim 14 (depends on 13) The method according to claim 13, wherein the providing comprises: generating triggering information instructing the background erase operation to be performed when the write count information exceeds the preset reference value; and generating a background erase operation command instructing the background erase operation to be performed on the at least one free block based on the triggering information. ### Claim 15 (depends on 14) The method according to claim 14, wherein the generating of the background erase operation command comprises generating the background erase operation command for a free block having a lowest erase operation count among a plurality of free blocks included in a free block list including information about addresses of the plurality free blocks included in the memory device. ### Claim 16 (depends on 12) The method according to claim 12, wherein, when a normal operation command is inputted from the memory controller while the background erase operation is performed, the memory device suspends the background erase operation in response to input of a confirm command of the normal operation command. ### Claim 17 A memory system comprising: a memory device including a plurality of memory blocks; and a controller configured to control, when accumulated size of data stored in the memory blocks becomes greater than storage capacity of a single memory block, the memory device to perform a background erase operation on one or more memory blocks storing invalid data among the memory blocks while the memory device is idle.