# US 2019/0318783 A1 · Memory module for platform with non-volatile storage

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0318783 A1
- Document ID: US20190318783A1
- Status: Published application
- Kind: A1
- Application number: 16/467,619
- Filed: 2017-11-20
- Published: 2019-10-17
- Earliest claimed: 2016-12-09
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Aws Shallal; Nigel Alvares; Sarvagya Kochak
- Web page: https://patentgrep.com/patent/US20190318783A1

## CPC

- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G11C 5/00: Details of stores covered by group G11C11/00
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 2207/2227: Standby or low power modes
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

## Claims

### Claim 1

A system comprising:
a non-volatile memory (NVM) data backup subsystem including non-volatile memory; and
a plurality of memory modules that are separate from the NVM data backup subsystem, wherein a first memory module of the memory modules comprises:
a plurality of first random access memory packages, each first random access memory package including a primary data port and a backup data port; and
a first storage interface circuit coupled to the backup data ports of the first random access memory packages, the first storage interface circuit offloading data from the first memory module in the event of a power loss by receiving data from the backup data ports of the first random access memory packages and transmitting the data to the NVM data backup subsystem.

### Claim 2 (depends on 1)

The system of claim 1, wherein the first memory module comprises:
a data backup connector;
wherein the first storage interface circuit transmits the data to the NVM data backup subsystem via the data backup connector.

### Claim 3 (depends on 2)

The system of claim 2, wherein the data backup connector is a cable connector.

### Claim 4 (depends on 2)

The system of claim 2, wherein the data backup connector is a dual in line memory module edge connector.

### Claim 5 (depends on 1)

The system of claim 1, wherein the first memory module comprises:
an edge connector at an edge of the first memory module; and
a plurality of data buffer circuits to buffer data between the edge connector and the primary data ports of the first random access memory packages,
wherein the data buffer circuits are turned off while the storage interface circuit is offloading data.

### Claim 6 (depends on 1)

The system of claim 1, wherein clock synchronization circuits in the first random access memory packages are turned off while the storage interface circuit is offloading data.

### Claim 7 (depends on 1)

The system of claim 1, wherein the first storage interface circuit comprises a serializer circuit to serialize the data received from the backup data ports of the first random access memory packages into serialized data, wherein the data is transmitted to the NVM data backup subsystem is the serialized data.

### Claim 8 (depends on 1)

The system of claim 1, wherein each first random access memory package comprises:
a random access memory core; and
multiplexing circuitry that is coupled to the random access memory core through a data access path, the multiplexing circuitry selectively coupling one of the primary data port and the backup data port to the data access path at a time.

### Claim 9 (depends on 1)

The system of claim 1, wherein the first storage interface circuit restores the data to the first memory module when power is restored by receiving the data from the NVM data backup subsystem and writing the data to the backup data ports of the random access memory packages.

### Claim 10 (depends on 1)

The system of claim 1, wherein a second memory module of the memory modules comprises:
a plurality of second random access memory packages, each second random access memory package including a primary data port and a backup data port; and
a second storage interface circuit coupled to the backup data ports of the second random access memory packages, the second storage interface circuit offloading data from the second memory module in event of the power loss by receiving data from the backup data ports of the second random access memory packages and transmitting the data to the NVM data backup subsystem.

### Claim 11 (depends on 10)

The system of claim 10, wherein the non-volatile memory subsystem comprises:
a non-volatile memory device that includes the non-volatile memory; and
a central backup controller to receive the data from the first memory module and to receive the data from the second memory module, the central backup controller writing the data from the first memory module and the data from the second memory module to the non-volatile memory device.

### Claim 12

A memory module comprising:
a plurality of random access memory packages, each including a primary data port and a backup data port; and
a storage interface circuit coupled to the backup data ports of the random access memory packages, the storage interface circuit to offload data from the memory module in the event of a power loss by receiving data from the backup data ports of the memory packages and transmitting the data to an external non-volatile memory (NVM) data backup subsystem that is separate from the memory module.

### Claim 13 (depends on 12)

The memory module of claim 12, wherein the memory module comprises:
a data backup connector;
wherein the storage interface circuit transmits the data to the external NVM data backup subsystem via the data backup connector.

### Claim 14 (depends on 13)

The memory module of claim 13, wherein the data backup connector is a ribbon cable connector.

### Claim 15 (depends on 13)

The memory module of claim 13, wherein the data backup connector is a dual in line memory module edge connector.

### Claim 16 (depends on 12)

The memory module of claim 12, further comprising:
an edge connector at an edge of the memory module; and
a plurality of data buffer circuits to buffer data between the edge connector and the primary data ports of the random access memory packages,
wherein the data buffer circuits are turned off while the storage interface circuit is offloading data.

### Claim 17 (depends on 12)

The memory module of claim 12, wherein a clock synchronization circuit in the random access memory packages is turned off while the storage interface circuit is offloading data.

### Claim 18 (depends on 12)

The memory module of claim 12, wherein the storage interface circuit comprises a serializer circuit to serialize the data received from the backup data ports of the random access memory packages into serialized data, wherein the data is transmitted to the external NVM data backup subsystem is the serialized data.

### Claim 19 (depends on 12)

The memory module of claim 12, wherein each random access memory package comprises:
a random access memory core; and
multiplexing circuitry that is coupled to the random access memory core through a data access path, the multiplexing circuitry selectively coupling one of the primary data port and the backup data port to the data access path at a time.

### Claim 20 (depends on 12)

The memory module of claim 12, wherein the storage interface circuit restores the data to the memory module when power is restored by receiving the data from the external NVM data backup subsystem and writing the data to the backup data ports of the random access memory packages.