# US 2019/0318781 A1 · Analog method for programming a phase change memory cell by means of identical electrical pulses

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- Number: US 2019/0318781 A1
- Document ID: US20190318781A1
- Status: Published application
- Kind: A1
- Application number: 16/296,834
- Filed: 2019-03-08
- Published: 2019-10-17
- Earliest claimed: 2018-03-09
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Inventors: Selina LA BARBERA; Niccolo CASTELLANI; Gabriele NAVARRO; Elisa VIANELLO
- Web page: https://patentgrep.com/patent/US20190318781A1

## CPC

- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for programming a phase change memory cell placed in an initial crystalline state, the memory cell being called of taking a plurality of resistance values belonging to a range of values called “programming window”, the method including parameterizing a lower limit of the programming window by applying to the memory cell a single gradual writing voltage pulse or a first series of identical gradual writing voltage pulses; progressively adjusting the resistance value of the memory cell by the following operations: a gradual erasing operation during which a series of identical gradual erasing voltage pulses is applied to the memory cell; a gradual writing operation during which a second series of identical gradual writing voltage pulses is applied to the memory cell; the gradual writing and gradual erasing voltage pulses have a width less than 50 ns.

## Claims

### Claim 1

A method for programming a phase change memory cell placed in an initial crystalline state, the memory cell being capable of taking a plurality of resistance values belonging to a range of values forming a programming window, the method comprising:
parameterizing a lower limit of the programming window by applying to the memory cell a single gradual writing voltage pulse or a first series of identical gradual writing voltage pulses;
progressively adjusting the resistance value of the memory cell by means of the following operations:
a gradual erasing operation during which a series of identical gradual erasing voltage pulses is applied to the memory cell, the gradual erasing voltage pulses being defined so as to lead to a progressive increase in the resistance value of the memory cell;
a gradual writing operation during which a second series of identical gradual writing voltage pulses is applied to the memory cell, the gradual writing voltage pulses being defined so as to lead to a progressive decrease in the resistance value of the memory cell;
the gradual writing and gradual erasing voltage pulses having a width less than 50 ns.

### Claim 2 (depends on 1)

The programming method according to claim 1, wherein the memory cell is placed in the initial crystalline state during an initialisation step, the gradual writing and gradual erasing voltage pulses being defined by an amplitude and a width determined during the initialisation step.

### Claim 3 (depends on 2)

The programming method according to claim 2, wherein the memory cell reaches an entirely erased state during the initialisation step when voltage pulses having a total erasing amplitude are applied to the memory cell, the gradual writing and gradual erasing voltage pulses each having an amplitude less than the total erasing amplitude.

### Claim 4 (depends on 3)

The programming method according to claim 3, wherein the amplitude (VSET_grad) of the gradual writing voltage pulses satisfies the following relationship:
V
melt
+
5
100

(
V
RESET

_

tot
-
V
melt
)
≤
V
SET

_

grad
≤
V
melt
+
30
100

(
V
RESET

_

tot
-
V
melt
)
where Vmelt is an amorphization beginning voltage and VRESET_tot is the total erasing amplitude.

### Claim 5 (depends on 3)

The programming method according to claim 3, wherein the amplitude (VRESET_grad) of the gradual erasing voltage pulses satisfies the following relationship:
V
melt
+
60
100

(
V
RESET

_

tot
-
V
melt
)
≤
V
RESET

_

grad
≤
V
melt
+
80
100

(
V
RESET

_

tot
-
V
melt
)
where Vmelt is an amorphization beginning voltage and VRESET_tot is the total erasing amplitude.

### Claim 6 (depends on 1)

The programming method according to claim 1, wherein the lower limit of the programming window is comprised between 15 kΩ and 30 kΩ.

### Claim 7 (depends on 1)

The programming method according to claim 1, wherein the memory cell comprises a chalcogenide-based or a chalcogenide alloy-based phase change material.