# US 2019/0318778 A1 · Operation control circuit and semiconductor memory device including the operation control circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318778 A1 - Document ID: US20190318778A1 - Status: Published application - Kind: A1 - Application number: 16/189,590 - Filed: 2018-11-13 - Published: 2019-10-17 - Earliest claimed: 2018-04-16 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: I Yeong JUNG; Geun Il LEE - Web page: https://patentgrep.com/patent/US20190318778A1 ## CPC - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/109: {Control signal input circuits} - G11C 11/40607: {Refresh operations in memory devices with an internal cache or data buffer} - G11C 11/40626: {Temperature related aspects of refresh operations} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered. ## Claims ### Claim 1 A semiconductor memory device comprising: a control signal generation circuit configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal; a period signal generation circuit configured to generate a periodically transited period signal in response to the control signal; and a selection circuit configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, further comprising: an input circuit configured to buffer the signal from the external device to output the buffered signal. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the control signal generation circuit enables the control signal when the mode signal is enabled and any one of the voltage detection signal and the temperature detection signal is enabled. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, wherein the control signal generation circuit disables the control signal when the mode signal is disabled, and the control signal generation circuit disables the control signal when the mode signal is enabled and the voltage detection signal and the temperature detection signal are disabled. ### Claim 5 (depends on 3) The semiconductor memory device of claim 3, wherein the period signal generation circuit generates the periodically transited period signal when the control signal is enabled. ### Claim 6 (depends on 3) The semiconductor memory device of claim 3, wherein the selection circuit outputs the buffered signal when the control signal is disabled, and the selection circuit outputs the period signal when the control signal is enabled. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, further comprising: a voltage detection circuit configured to enable the voltage detection signal when a voltage used in the semiconductor memory device becomes higher than a set voltage; and a temperature detection circuit configured to enable the temperature detection signal when a temperature in the semiconductor memory device becomes higher than a set temperature. ### Claim 8 (depends on 1) The semiconductor memory device of claim 1, wherein the mode signal comprises a self-refresh signal. ### Claim 9 A semiconductor memory device comprising: a selection circuit configured to output a periodically transited period signal in place of a signal from an external device that is buffered when a voltage in a self-refresh operation is higher than a set voltage and/or a temperature in the self-refresh operation is higher than a set temperature. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, further comprising: an input circuit configured to buffer the signal from the external device to output the buffered signal. ### Claim 11 (depends on 9) The semiconductor memory device of claim 9, wherein the selection circuit outputs the period signal in place of the buffered signal when the voltage in a self-refresh operation becomes higher than the set voltage and/or the temperature in the self-refresh operation becomes higher than the set temperature under a condition that a self-refresh signal is enabled. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, wherein the selection circuit outputs the buffered signal to the signal transmission circuit when the control signal is disabled, and the selection circuit outputs the period signal to the signal transmission circuit when the control signal is enabled. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, further comprising an operation control circuit configured to generate the enabled control signal when the voltage in a self-refresh operation becomes higher than the set voltage and/or the temperature in the self-refresh operation becomes higher than the set temperature under the condition that the self-refresh signal is enabled, and configured to generate the period signal when the control signal is enabled. ### Claim 14 (depends on 13) The semiconductor memory device of claim 13, wherein the operation control circuit comprises: a voltage detection circuit configured to enable a voltage detection signal when the voltage in the refresh operation becomes higher than the set voltage; a temperature detection circuit configured to enable a temperature detection signal when the temperature in the refresh operation becomes higher than the set temperature; a control signal generation circuit configured to enable the control signal when the self-refresh signal is enabled and any one of the voltage detection signal and the temperature detection signal is enabled; and a period signal generation circuit configured to generate the period signal when the control signal is enabled. ### Claim 15 An operation control circuit comprising: a control signal generation circuit configured to generate a control signal when a voltage in a self-refresh operation is higher than a set voltage and/or a temperature in the self-refresh operation is higher than a set temperature; and a period signal generation circuit configured to generate a periodically transited period signal in response to the control signal. ### Claim 16 (depends on 15) The operation control circuit of claim 15, wherein the control signal controls a selection circuit to output the periodically transited period signal in place of a signal from an external device that is buffered. ### Claim 17 (depends on 15) The operation control circuit of claim 15, wherein the control signal generation circuit disables the control signal in a normal operation, and the control signal generation circuit disables the control signal when the voltage detection signal and the temperature detection signal are disabled in a self-refresh operation. ### Claim 18 (depends on 15) The operation control circuit of claim 15, wherein the period signal generation circuit generates the periodically transited period signal when the control signal is enabled. ### Claim 19 (depends on 16) The operation control circuit of claim 16, wherein the selection circuit outputs the buffered signal when the control signal is disabled, and the selection circuit outputs the period signal when the control signal is enabled. ### Claim 20 (depends on 15) The operation control circuit of claim 15, further comprising: a voltage detection circuit configured to enable the voltage detection signal when the voltage used in the semiconductor memory device becomes higher than the set voltage; and a temperature detection circuit configured to enable the temperature detection signal when the temperature in the semiconductor memory device becomes higher than the set temperature.